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ARM: dts: rockchip: Add rk3126c-evb-ddr3-v10-linux-slc

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add: rk3126c-evb-ddr3-v10-linux-slc.dts
modify: Makefile add rk3126c-evb-ddr3-v10-linux-slc.dtb

Change-Id: I1cc79bb73ade9f69b30f1f00cdcb714053c1d12c
Signed-off-by: Jun Zeng <jun.zeng@rock-chips.com>
This commit is contained in:
Jun Zeng
2022-05-30 17:07:45 +08:00
committed by Tao Huang
parent 06486f152f
commit e11f71a131
2 changed files with 33 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@@ -1010,6 +1010,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3126c-evb-ddr3-v10-linux.dtb \
rk3126c-evb-ddr3-v10-linux-slc.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \

32
arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux-slc.dts Normal file
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@@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3126c-evb-ddr3-v10-linux.dts"
/ {
chosen {
bootargs = "ubi.mtd=7 root=ubi0:rootfs rootfstype=ubifs";
};
};
&emmc {
status = "disabled";
};
&nandc {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&cru SCLK_NANDC>;
assigned-clock-rates = <120000000>;
nand@0 {
reg = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <16>;
nand-ecc-step-size = <1024>;
};
};