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clk: rockchip: rk3036: export the hevc core clock

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The clock hevc core will be used to drive the hevc decoder.

Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Randy Li
2017-10-20 14:38:09 +08:00
committed by Tao Huang
parent 39389fb7aa
commit e35fd036b3
2 changed files with 5 additions and 1 deletions
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5
drivers/clk/rockchip/clk-rk3036.c
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@@ -101,8 +101,11 @@ static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
}
static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
RK3036_CPUCLK_RATE(1200000000, 4),
RK3036_CPUCLK_RATE(1008000000, 4),
RK3036_CPUCLK_RATE(816000000, 4),
RK3036_CPUCLK_RATE(600000000, 4),
RK3036_CPUCLK_RATE(408000000, 4),
RK3036_CPUCLK_RATE(312000000, 4),
};
@@ -270,7 +273,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 6, GFLAGS),

1
include/dt-bindings/clock/rk3036-cru.h
View File

@@ -55,6 +55,7 @@
#define ACLK_VCODEC 208
#define ACLK_CPU 209
#define ACLK_PERI 210
#define ACLK_HEVC 211
/* pclk gates */
#define PCLK_GPIO0 320