Merge commit 'ae9109eca6dec79d64974d8c197ebb31e5519bcd'

* commit 'ae9109eca6dec79d64974d8c197ebb31e5519bcd':
  drm/rockchip: dw-dp: protect panel status when show logo
  mtd: spi-nor: puya: support PY25Q64LB
  soc: rockchip: thunderboot_mmc: Send CMD12 after transmission completion
  arm64: dts: rockchip: rv1126b-evb: set venc-supply for evb1/evb4
  PCI: rockchip: dw_ep: Support building as a module when dma_test disabled
  PCI: rockchip: dw: Add unregister_gpio_hotplug_slot
  PCI: rockchip: dw: Add PCIE_DW_ROCKCHIP_RC_DMATEST macro limit for dma test unregister
  arm64: configs: Add rv1126b-fastboot.config
  ASoC: rockchip: multi-dais: Use the frame burst

Change-Id: Ib4b7a4c63e1889940e08dcd858d9f27527f0e962
This commit is contained in:
Tao Huang
2025-08-26 19:30:22 +08:00
9 changed files with 68 additions and 23 deletions

View File

@@ -469,6 +469,10 @@
rknpu-supply = <&vdd_npu>;
};
&rkvenc {
venc-supply = <&vdd_logic>;
};
&route_dsi {
status = "okay";
};

View File

@@ -477,6 +477,10 @@
rknpu-supply = <&vdd_npu>;
};
&rkvenc {
venc-supply = <&vdd_logic>;
};
&rockchip_suspend {
status = "okay";

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@@ -0,0 +1,17 @@
CONFIG_DAX=y
CONFIG_EROFS_FS=y
CONFIG_LIBCRC32C=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_RAMDISK=y
CONFIG_ROCKCHIP_THUNDER_BOOT=y
CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y
# CONFIG_EROFS_FS_DEBUG is not set
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
CONFIG_FS_DAX=y
CONFIG_INITCALL_ASYNC=y
# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set
# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP is not set

View File

@@ -3309,6 +3309,8 @@ static int dw_dp_loader_protect(struct rockchip_drm_sub_dev *sub_dev, bool on)
struct dw_dp *dp = container_of(sub_dev, struct dw_dp, sub_dev);
dp->is_loader_protect = true;
if (dp->panel)
rockchip_drm_panel_loader_protect(dp->panel, on);
_dw_dp_loader_protect(dp, on);
if (dp->right)
_dw_dp_loader_protect(dp->right, on);

View File

@@ -23,6 +23,9 @@ static const struct flash_info puya_parts[] = {
{ "PY25Q256HB", INFO(0x852019, 0, 64 * 1024, 512)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
{ "PY25Q64LB", INFO(0x856517, 0, 64 * 1024, 128)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ "PY25Q128LA", INFO(0x856518, 0, 64 * 1024, 256)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },

View File

@@ -289,6 +289,7 @@ static int rockchip_pcie_get_io_resource(struct platform_device *pdev,
if (IS_ERR(rockchip->pci.dbi_base))
return PTR_ERR(rockchip->pci.dbi_base);
rockchip->pci.atu_base = rockchip->pci.dbi_base + DEFAULT_DBI_ATU_OFFSET;
rockchip->pci.atu_size = SZ_4K;
rockchip->dbi_base_physical = dbi_res->start;
ret = device_property_read_u32(dev, "num-ib-windows", &rockchip->num_ib_windows);
@@ -937,9 +938,6 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
u32 reg, val;
int ret, retries, i;
/* Detecting ATU features to achieve DWC ATU interface development */
dw_pcie_iatu_detect(&rockchip->pci);
if (dw_pcie_link_up(&rockchip->pci))
goto already_linkup;
else
@@ -1246,13 +1244,14 @@ static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dm
static int rockchip_pcie_init_dma_trx(struct rockchip_pcie *rockchip)
{
struct dw_pcie *pci = &rockchip->pci;
rockchip->dma_obj = pcie_dw_dmatest_register(pci->dev, true);
if (IS_ERR(rockchip->dma_obj)) {
dev_err(rockchip->pci.dev, "failed to prepare dmatest\n");
return -EINVAL;
} else if (rockchip->dma_obj) {
if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST)) {
rockchip->dma_obj = pcie_dw_dmatest_register(rockchip->pci.dev, true);
if (IS_ERR(rockchip->dma_obj)) {
dev_err(rockchip->pci.dev, "failed to prepare dmatest\n");
return -EINVAL;
}
}
if (rockchip->dma_obj) {
rockchip->dma_obj->start_dma_func = rockchip_pcie_start_dma_dwc;
rockchip->dma_obj->config_dma_func = rockchip_pcie_config_dma_dwc;
rockchip->dma_obj->get_dma_status = rockchip_pcie_get_dma_status;
@@ -1263,7 +1262,7 @@ static int rockchip_pcie_init_dma_trx(struct rockchip_pcie *rockchip)
static void rockchip_pcie_deinit_dma_trx(struct rockchip_pcie *rockchip)
{
if (rockchip->dma_obj)
if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST) && rockchip->dma_obj)
pcie_dw_dmatest_unregister(rockchip->dma_obj);
}

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@@ -573,13 +573,13 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
if (!rk_pcie_udma_enabled(rk_pcie))
return 0;
#ifdef PCIE_DW_ROCKCHIP_RC_DMATEST
rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
if (IS_ERR(rk_pcie->dma_obj)) {
dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
return -EINVAL;
if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST)) {
rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
if (IS_ERR(rk_pcie->dma_obj)) {
dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
return -EINVAL;
}
}
#endif
if (!rk_pcie->dma_obj)
return 0;
@@ -1700,7 +1700,7 @@ static int rk_pcie_really_probe(void *p)
if (ret && !rk_pcie->slot_pluggable)
goto deinit_irq_and_wq;
if (rk_pcie->slot_pluggable) {
if (IS_BUILTIN(CONFIG_PCIE_DW_ROCKCHIP) && rk_pcie->slot_pluggable) {
rk_pcie->hp_slot.plat_ops = &rk_pcie_gpio_hp_plat_ops;
rk_pcie->hp_slot.np = rk_pcie->pci->dev->of_node;
rk_pcie->hp_slot.slot_nr = rk_pcie->pci->pp.bridge->busnr;
@@ -1802,7 +1802,8 @@ static int rk_pcie_remove(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_NO_GKI)) dw_pcie_host_deinit(&rk_pcie->pci->pp);
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xffffffff);
destroy_workqueue(rk_pcie->hot_rst_wq);
pcie_dw_dmatest_unregister(rk_pcie->dma_obj);
if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST))
pcie_dw_dmatest_unregister(rk_pcie->dma_obj);
rockchip_pcie_debugfs_exit(rk_pcie);
if (rk_pcie->irq_domain) {
int virq, j;
@@ -1816,6 +1817,9 @@ static int rk_pcie_remove(struct platform_device *pdev)
irq_domain_remove(rk_pcie->irq_domain);
}
if (IS_BUILTIN(CONFIG_PCIE_DW_ROCKCHIP) && rk_pcie->slot_pluggable)
unregister_gpio_hotplug_slot(&rk_pcie->hp_slot);
device_init_wakeup(dev, false);
rk_pcie_host_unconfig(rk_pcie);

View File

@@ -17,6 +17,8 @@
#include <linux/soc/rockchip/rockchip_thunderboot_crypto.h>
#define SDMMC_CTRL 0x000
#define SDMMC_CMDARG 0x028
#define SDMMC_CMD 0x02c
#define SDMMC_RINTSTS 0x044
#define SDMMC_STATUS 0x048
#define SDMMC_BMOD 0x080
@@ -84,6 +86,18 @@ static int rk_tb_mmc_thread(void *p)
writel(0, regs + SDMMC_BMOD);
writel(0, regs + SDMMC_DBADDR);
/* Send CMD12 to stop transmission */
writel(0xffffffff, regs + SDMMC_RINTSTS);
writel(0, regs + SDMMC_CMDARG);
writel(0xa000414c, regs + SDMMC_CMD);
if (readl_poll_timeout(regs + SDMMC_RINTSTS, status,
!(status & BIT(2)), 100,
11 * USEC_PER_MSEC)) {
dev_err(dev, "Send CMD12 timeout!\n");
goto out;
}
/* Parse ramdisk addr and help start decompressing */
if (rds && rdd) {
struct resource src, dst;

View File

@@ -630,7 +630,6 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
struct dma_slave_config slave_config;
snd_pcm_format_t format;
unsigned int *maps;
int frame_bytes;
int ret, num, i, sz;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
@@ -638,7 +637,6 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
else
maps = pcm->mdais->capture_channel_maps;
format = params_format(params);
frame_bytes = snd_pcm_format_size(format, params_channels(params));
num = pcm->mdais->num_dais;
for (i = 0; i < num; i++) {
@@ -661,11 +659,11 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
sz = snd_pcm_format_size(format, maps[i]);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
chan = pcm->tx_chans[i];
if (sz && (frame_bytes - sz) > 0)
if (sz)
slave_config.dst_maxburst = sz / slave_config.dst_addr_width;
} else {
chan = pcm->rx_chans[i];
if (sz && (frame_bytes - sz) > 0)
if (sz)
slave_config.src_maxburst = sz / slave_config.src_addr_width;
}
if (!chan)