mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-05 02:21:52 +09:00
Merge commit 'ae9109eca6dec79d64974d8c197ebb31e5519bcd'
* commit 'ae9109eca6dec79d64974d8c197ebb31e5519bcd': drm/rockchip: dw-dp: protect panel status when show logo mtd: spi-nor: puya: support PY25Q64LB soc: rockchip: thunderboot_mmc: Send CMD12 after transmission completion arm64: dts: rockchip: rv1126b-evb: set venc-supply for evb1/evb4 PCI: rockchip: dw_ep: Support building as a module when dma_test disabled PCI: rockchip: dw: Add unregister_gpio_hotplug_slot PCI: rockchip: dw: Add PCIE_DW_ROCKCHIP_RC_DMATEST macro limit for dma test unregister arm64: configs: Add rv1126b-fastboot.config ASoC: rockchip: multi-dais: Use the frame burst Change-Id: Ib4b7a4c63e1889940e08dcd858d9f27527f0e962
This commit is contained in:
@@ -469,6 +469,10 @@
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rknpu-supply = <&vdd_npu>;
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};
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&rkvenc {
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venc-supply = <&vdd_logic>;
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};
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&route_dsi {
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status = "okay";
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};
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@@ -477,6 +477,10 @@
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rknpu-supply = <&vdd_npu>;
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};
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&rkvenc {
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venc-supply = <&vdd_logic>;
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};
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&rockchip_suspend {
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status = "okay";
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17
arch/arm64/configs/rv1126b-fastboot.config
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17
arch/arm64/configs/rv1126b-fastboot.config
Normal file
@@ -0,0 +1,17 @@
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CONFIG_DAX=y
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CONFIG_EROFS_FS=y
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CONFIG_LIBCRC32C=y
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CONFIG_ROCKCHIP_HW_DECOMPRESS=y
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CONFIG_ROCKCHIP_RAMDISK=y
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CONFIG_ROCKCHIP_THUNDER_BOOT=y
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CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y
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# CONFIG_EROFS_FS_DEBUG is not set
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# CONFIG_EROFS_FS_XATTR is not set
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# CONFIG_EROFS_FS_ZIP is not set
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CONFIG_FS_DAX=y
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CONFIG_INITCALL_ASYNC=y
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# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
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CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
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CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
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# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set
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# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP is not set
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@@ -3309,6 +3309,8 @@ static int dw_dp_loader_protect(struct rockchip_drm_sub_dev *sub_dev, bool on)
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struct dw_dp *dp = container_of(sub_dev, struct dw_dp, sub_dev);
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dp->is_loader_protect = true;
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if (dp->panel)
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rockchip_drm_panel_loader_protect(dp->panel, on);
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_dw_dp_loader_protect(dp, on);
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if (dp->right)
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_dw_dp_loader_protect(dp->right, on);
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@@ -23,6 +23,9 @@ static const struct flash_info puya_parts[] = {
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{ "PY25Q256HB", INFO(0x852019, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "PY25Q64LB", INFO(0x856517, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "PY25Q128LA", INFO(0x856518, 0, 64 * 1024, 256)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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@@ -289,6 +289,7 @@ static int rockchip_pcie_get_io_resource(struct platform_device *pdev,
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if (IS_ERR(rockchip->pci.dbi_base))
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return PTR_ERR(rockchip->pci.dbi_base);
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rockchip->pci.atu_base = rockchip->pci.dbi_base + DEFAULT_DBI_ATU_OFFSET;
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rockchip->pci.atu_size = SZ_4K;
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rockchip->dbi_base_physical = dbi_res->start;
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ret = device_property_read_u32(dev, "num-ib-windows", &rockchip->num_ib_windows);
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@@ -937,9 +938,6 @@ static int rockchip_pcie_config_host(struct rockchip_pcie *rockchip)
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u32 reg, val;
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int ret, retries, i;
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/* Detecting ATU features to achieve DWC ATU interface development */
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dw_pcie_iatu_detect(&rockchip->pci);
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if (dw_pcie_link_up(&rockchip->pci))
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goto already_linkup;
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else
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@@ -1246,13 +1244,14 @@ static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dm
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static int rockchip_pcie_init_dma_trx(struct rockchip_pcie *rockchip)
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{
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struct dw_pcie *pci = &rockchip->pci;
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rockchip->dma_obj = pcie_dw_dmatest_register(pci->dev, true);
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if (IS_ERR(rockchip->dma_obj)) {
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dev_err(rockchip->pci.dev, "failed to prepare dmatest\n");
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return -EINVAL;
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} else if (rockchip->dma_obj) {
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if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST)) {
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rockchip->dma_obj = pcie_dw_dmatest_register(rockchip->pci.dev, true);
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if (IS_ERR(rockchip->dma_obj)) {
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dev_err(rockchip->pci.dev, "failed to prepare dmatest\n");
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return -EINVAL;
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}
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}
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if (rockchip->dma_obj) {
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rockchip->dma_obj->start_dma_func = rockchip_pcie_start_dma_dwc;
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rockchip->dma_obj->config_dma_func = rockchip_pcie_config_dma_dwc;
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rockchip->dma_obj->get_dma_status = rockchip_pcie_get_dma_status;
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@@ -1263,7 +1262,7 @@ static int rockchip_pcie_init_dma_trx(struct rockchip_pcie *rockchip)
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static void rockchip_pcie_deinit_dma_trx(struct rockchip_pcie *rockchip)
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{
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if (rockchip->dma_obj)
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if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST) && rockchip->dma_obj)
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pcie_dw_dmatest_unregister(rockchip->dma_obj);
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}
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@@ -573,13 +573,13 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
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if (!rk_pcie_udma_enabled(rk_pcie))
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return 0;
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#ifdef PCIE_DW_ROCKCHIP_RC_DMATEST
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rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
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if (IS_ERR(rk_pcie->dma_obj)) {
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dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
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return -EINVAL;
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if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST)) {
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rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true);
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if (IS_ERR(rk_pcie->dma_obj)) {
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dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
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return -EINVAL;
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}
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}
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#endif
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if (!rk_pcie->dma_obj)
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return 0;
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@@ -1700,7 +1700,7 @@ static int rk_pcie_really_probe(void *p)
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if (ret && !rk_pcie->slot_pluggable)
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goto deinit_irq_and_wq;
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if (rk_pcie->slot_pluggable) {
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if (IS_BUILTIN(CONFIG_PCIE_DW_ROCKCHIP) && rk_pcie->slot_pluggable) {
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rk_pcie->hp_slot.plat_ops = &rk_pcie_gpio_hp_plat_ops;
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rk_pcie->hp_slot.np = rk_pcie->pci->dev->of_node;
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rk_pcie->hp_slot.slot_nr = rk_pcie->pci->pp.bridge->busnr;
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@@ -1802,7 +1802,8 @@ static int rk_pcie_remove(struct platform_device *pdev)
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if (IS_ENABLED(CONFIG_NO_GKI)) dw_pcie_host_deinit(&rk_pcie->pci->pp);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xffffffff);
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destroy_workqueue(rk_pcie->hot_rst_wq);
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pcie_dw_dmatest_unregister(rk_pcie->dma_obj);
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if (IS_ENABLED(CONFIG_PCIE_DW_ROCKCHIP_RC_DMATEST))
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pcie_dw_dmatest_unregister(rk_pcie->dma_obj);
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rockchip_pcie_debugfs_exit(rk_pcie);
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if (rk_pcie->irq_domain) {
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int virq, j;
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@@ -1816,6 +1817,9 @@ static int rk_pcie_remove(struct platform_device *pdev)
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irq_domain_remove(rk_pcie->irq_domain);
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}
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if (IS_BUILTIN(CONFIG_PCIE_DW_ROCKCHIP) && rk_pcie->slot_pluggable)
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unregister_gpio_hotplug_slot(&rk_pcie->hp_slot);
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device_init_wakeup(dev, false);
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rk_pcie_host_unconfig(rk_pcie);
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@@ -17,6 +17,8 @@
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#include <linux/soc/rockchip/rockchip_thunderboot_crypto.h>
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#define SDMMC_CTRL 0x000
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#define SDMMC_CMDARG 0x028
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#define SDMMC_CMD 0x02c
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#define SDMMC_RINTSTS 0x044
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#define SDMMC_STATUS 0x048
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#define SDMMC_BMOD 0x080
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@@ -84,6 +86,18 @@ static int rk_tb_mmc_thread(void *p)
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writel(0, regs + SDMMC_BMOD);
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writel(0, regs + SDMMC_DBADDR);
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/* Send CMD12 to stop transmission */
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writel(0xffffffff, regs + SDMMC_RINTSTS);
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writel(0, regs + SDMMC_CMDARG);
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writel(0xa000414c, regs + SDMMC_CMD);
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if (readl_poll_timeout(regs + SDMMC_RINTSTS, status,
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!(status & BIT(2)), 100,
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11 * USEC_PER_MSEC)) {
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dev_err(dev, "Send CMD12 timeout!\n");
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goto out;
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}
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/* Parse ramdisk addr and help start decompressing */
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if (rds && rdd) {
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struct resource src, dst;
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@@ -630,7 +630,6 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
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struct dma_slave_config slave_config;
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snd_pcm_format_t format;
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unsigned int *maps;
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int frame_bytes;
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int ret, num, i, sz;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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@@ -638,7 +637,6 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
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else
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maps = pcm->mdais->capture_channel_maps;
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format = params_format(params);
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frame_bytes = snd_pcm_format_size(format, params_channels(params));
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num = pcm->mdais->num_dais;
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for (i = 0; i < num; i++) {
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@@ -661,11 +659,11 @@ static int dmaengine_mpcm_hw_params(struct snd_soc_component *component,
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sz = snd_pcm_format_size(format, maps[i]);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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chan = pcm->tx_chans[i];
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if (sz && (frame_bytes - sz) > 0)
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if (sz)
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slave_config.dst_maxburst = sz / slave_config.dst_addr_width;
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} else {
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chan = pcm->rx_chans[i];
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if (sz && (frame_bytes - sz) > 0)
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if (sz)
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slave_config.src_maxburst = sz / slave_config.src_addr_width;
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}
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if (!chan)
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