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clk: rockchip: rk3588: add 786M for AUPLL init

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ic9b76bc29cf07593a94deaeeaaecd81d5bdbd649
This commit is contained in:
Elaine Zhang
2021-11-12 09:27:57 +08:00
committed by Tao Huang
parent 72d54feee5
commit e5277633c6
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3588.c
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@@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(408000000, 2, 272, 3, 0),