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arm64: dts: rockchip: rk3528: set hdmi ddc scl rate as 50KHz

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The original 100khz rate is prone to ddc communication
error on some TVs. The scl rate was reduced to 50khz
by referring to competitor.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I51c3307566b68932e8ab9f1cb6a8ba47d03e7110
This commit is contained in:
Algea Cao
2023-04-02 19:57:24 +08:00
committed by Tao Huang
parent 50864b4004
commit e53e7c4bc5
1 changed files with 2 additions and 0 deletions
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2
arch/arm64/boot/dts/rockchip/rk3528.dtsi
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@@ -1505,6 +1505,8 @@
<&cru CLK_CEC_HDMI>,
<&inno_hdmiphy_clk>;
clock-names = "iahb", "isfr", "cec", "dclk_vp0";
ddc-i2c-scl-high-time-ns = <9625>;
ddc-i2c-scl-low-time-ns = <10000>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
pinctrl-names = "default", "idle";