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vpp: sr: disable more latch ctrl for SR0 [1/1]

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PD#TV-7673

Problem:
SR0 register enabled the latch function, it will cause
frame size setting out of sync when bypass sr0.

Solution:
Disable the latch option.

Verify:
Verified with X301

Change-Id: Ibfc4c5f8f695757ddd7d7d9e50e4b5be23268388
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2019-08-03 01:58:29 +08:00
committed by Luan Yuan
parent abb6df9408
commit e60c74ffd2
1 changed files with 7 additions and 1 deletions
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8
drivers/amlogic/media/video_sink/video.c
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@@ -13254,11 +13254,17 @@ static int __init video_early_init(void)
/* disable latch for sr core0/1 scaler */
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
WRITE_VCBUS_REG_BITS(
SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1);
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B))
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 0, 1);
/* TODO: check if the bit8 is available */
/* WRITE_VCBUS_REG_BITS( */
/* SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1); */
}
return 0;
}