shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3368: add ddr 2T mode control

Browse Source 
Change-Id: I813a540ea0e7d018fb913df1ac760880d2d6dd11
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
2019-11-06 18:18:45 +08:00
committed by Tao Huang
parent 721c9a683b
commit e671d67d33
3 changed files with 7 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt
View File

@@ -50,6 +50,8 @@ Required properties:
- phy_odt : define the phy odt in ohm, default value isPHY_RTT_279ohm
- ddr_2t : define the uptcl CMD/CLK 2T mode, default value is ENABLE_DDR_2T.
the driver strength and odt value are defined at include/dt-bindings/dram/rockchip,rk3368.h
Example:
@@ -73,5 +75,6 @@ Example:
phy_cmd_drv = <PHY_RON_34ohm>;
phy_dqs_drv = <PHY_RON_34ohm>;
phy_odt = <PHY_RTT_279ohm>;
ddr_2t = <ENABLE_DDR_2T>;
};
};

1
arch/arm64/boot/dts/rockchip/rk3368-dram-default-timing.dtsi
View File

@@ -61,5 +61,6 @@
phy_cmd_drv = <PHY_RON_34ohm>;
phy_dqs_drv = <PHY_RON_34ohm>;
phy_odt = <PHY_RTT_279ohm>;
ddr_2t = <ENABLE_DDR_2T>;
};
};

3
include/dt-bindings/memory/rk3368-dram.h
View File

@@ -103,4 +103,7 @@
#define PHY_RTT_80ohm (14)
#define PHY_RTT_74ohm (15)
#define ENABLE_DDR_2T (1)
#define DISABLE_DDR_2T (0)
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/