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drm/rockchip: vop2: Do not clear wb intr status when commit new wb
If a new wb commit is too close to the timing of wb dma complete, clearing the wb intr status will lose the wb dma complete status. In this case, the software process is as follows: vop2_wb_commit() -> vop2_wb_irqs_enable() -> Clear wb intr -> vop3_sys_isr()/vop2_isr() -> vop2_read_and_clear_wb_irqs() Since we had cleared the intr in vop2_wb_irqs_enable(), the value read by vop2_read_and_clear_wb_irqs() is 0, and we have lost the interrupt status. Change-Id: I93bf7bd8b57336c7bb64353ce935a6991f93742b Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
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@@ -3948,7 +3948,6 @@ static void vop2_wb_irqs_enable(struct vop2 *vop2)
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if (is_vop3(vop2))
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irqs |= WB_COMPLETE_INTR;
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VOP_INTR_SET_TYPE(vop2, intr, clear, irqs, 1);
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VOP_INTR_SET_TYPE(vop2, intr, enable, irqs, 1);
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}
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