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clk: rockchip: fix to SIP_V2 for rk3288

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Fixes: d2b92a90ea ("clk: rockchip: support setting ddr clock via SCPI and SIP Version 2 APIs")

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I7521443f50dbe3049fd8a08c769a74f5e364334a
This commit is contained in:
Jianqun Xu
2022-11-18 17:39:49 +08:00
committed by Tao Huang
parent a6a8f8d0a3
commit e733a7a8b3
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3288.c
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@@ -339,7 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
ROCKCHIP_DDRCLK_SIP),
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),