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ARM64: dts: rk3399: assign clk parent and rate for SCLK_EMMC

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Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.

Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2016-04-25 10:35:23 +08:00
committed by Tao Huang
parent 861969884f
commit e944f54685
1 changed files with 1 additions and 0 deletions
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arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -297,6 +297,7 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-parents = <&cru PLL_CPLL>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";