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clk: rockchip: rk1808: fix mmc clock mux configuration

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The mmc_clk has four selection for parent pll. The original
configuration fix the parent to GPLL that causes the mmc_clk can't
assign to a precision of 400KHz.

[    6.569962 ] mmc_host mmc2: Bus speed (slot 0) = 2320312Hz (slot req
400000Hz, actual 386718HZ div = 3)

Change-Id: Ie3f74de79ac1e5f455e829b1b361200ad8b33db2
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
This commit is contained in:
Ziyuan Xu
2018-10-12 14:49:47 +08:00
committed by Tao Huang
parent 237c632223
commit ea92b57bc0
1 changed files with 15 additions and 15 deletions
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30
drivers/clk/rockchip/clk-rk1808.c
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@@ -603,12 +603,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_sfc", 0,
RK1808_CLKGATE_CON(9), 13, GFLAGS),
MUX(0, "clk_sdio_src", mux_gpll_cpll_npll_24m_p, 0,
RK1808_CLKSEL_CON(22), 14, 2, MFLAGS),
COMPOSITE_NOMUX(SCLK_SDIO_DIV, "clk_sdio_div", "clk_sdio_src", CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(22), 0, 8, DFLAGS,
COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(22), 14, 2, MFLAGS, 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE_NOMUX(SCLK_SDIO_DIV50, "clk_sdio_div50", "clk_sdio_src", CLK_IGNORE_UNUSED,
COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(22), 14, 2, MFLAGS,
RK1808_CLKSEL_CON(23), 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 2, GFLAGS),
COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -618,12 +618,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK1808_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK1808_SDIO_CON1, 1),
MUX(0, "clk_emmc_src", mux_gpll_cpll_npll_24m_p, 0,
RK1808_CLKSEL_CON(24), 14, 2, MFLAGS),
COMPOSITE_NOMUX(SCLK_EMMC_DIV, "clk_emmc_div", "clk_emmc_src", CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(24), 0, 8, DFLAGS,
COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div",
mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(24), 14, 2, MFLAGS, 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_EMMC_DIV50, "clk_emmc_div50", "clk_emmc_src", CLK_IGNORE_UNUSED,
COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(24), 14, 2, MFLAGS,
RK1808_CLKSEL_CON(25), 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
@@ -632,12 +632,12 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK1808_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK1808_EMMC_CON1, 1),
MUX(0, "clk_sdmmc_src", mux_gpll_cpll_npll_24m_p, 0,
RK1808_CLKSEL_CON(20), 14, 2, MFLAGS),
COMPOSITE_NOMUX(SCLK_SDMMC_DIV, "clk_sdmmc_div", "clk_sdmmc_src", CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(20), 0, 8, DFLAGS,
COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 7, GFLAGS),
COMPOSITE_NOMUX(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", "clk_sdmmc_src", CLK_IGNORE_UNUSED,
COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50",
mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(20), 14, 2, MFLAGS,
RK1808_CLKSEL_CON(21), 0, 8, DFLAGS,
RK1808_CLKGATE_CON(9), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,