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ARM: dts: rockchip: add isp nodes for rv1106

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Change-Id: I93e20fccdd7269efac7e22eb7a83bbfea3ea22c3
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2022-03-08 17:20:22 +08:00
committed by Tao Huang
parent 4cfa4a1773
commit ead9f87f94
1 changed files with 38 additions and 0 deletions
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38
arch/arm/boot/dts/rv1106.dtsi
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@@ -95,6 +95,30 @@
};
};
rkisp_vir0: rkisp-vir0 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir1: rkisp-vir1 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir2: rkisp-vir2 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir3: rkisp-vir3 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -755,6 +779,20 @@
status = "disabled";
};
rkisp: rkisp@ffa00000 {
compatible = "rockchip,rv1106-rkisp";
reg = <0xffa00000 0x7f00>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
<&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>;
clock-names = "aclk_isp", "hclk_isp",
"clk_isp_core", "clk_isp_core_vicap";
status = "disabled";
};
gmac: ethernet@ffa80000 {
compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
reg = <0xffa80000 010000>;