arm64: dts: rockchip: add rk3576-evb1-v10-ipc-3x-linux.dts

Change-Id: I7eba699ffba9d7800b873121150fc40f2c81ba8e
Signed-off-by: LiuDiMing Lin <fenrir.lin@rock-chips.com>
This commit is contained in:
LiuDiMing Lin
2024-04-19 15:39:24 +08:00
committed by Tao Huang
parent a7377e78ec
commit ebb1606c2a
3 changed files with 403 additions and 0 deletions

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@@ -242,6 +242,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-android9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-edp-NV140QUM-N61.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-hdmi2dp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-image-reverse-demo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-ipc-3x-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-linux-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-lontium-hdmiin.dtb

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@@ -0,0 +1,386 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
&csi2_dphy1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx464_out0>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy1_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&csi2_dphy2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx464_out1>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy2_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&csi2_dphy4 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam3: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx464_out2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy4_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-0 = <&i2c5m3_xfer>;
/* module 77/79 0x1a 78/80 0x36 */
imx464_0: imx464-0@1a {
compatible = "sony,imx464";
status = "okay";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk1m0_clk1>;
avdd-supply = <&vcc_mipicsi0>;
pwdn-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT1980-PX1";
rockchip,camera-module-lens-name = "SHG102";
port {
imx464_out0: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
imx464_1: imx464-1@36 {
compatible = "sony,imx464";
status = "okay";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
avdd-supply = <&vcc_mipicsi0>;
pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;/* hw not connect as default */
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT1980-PX1";
rockchip,camera-module-lens-name = "SHG102";
port {
imx464_out1: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2>;
};
};
};
};
&i2c8 {
status = "okay";
pinctrl-0 = <&i2c8m2_xfer>;
/* 77/79 0x1a 78/80 0x36 */
imx464_2: imx464-2@1a {
compatible = "sony,imx464";
status = "okay";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M2>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk2m0_clk2>;
avdd-supply = <&vcc_mipicsi1>;
pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT1980-PX1";
rockchip,camera-module-lens-name = "SHG102";
port {
imx464_out2: endpoint {
remote-endpoint = <&mipi_in_ucam3>;
data-lanes = <1 2>;
};
};
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy1_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in1>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy2_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy4_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in3>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
cif_mipi_in1: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
mipi1_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir0>;
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir1>;
};
};
};
&rkcif_mipi_lvds3 {
status = "okay";
port {
cif_mipi_in3: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mipi_lvds3_sditf {
status = "okay";
port {
mipi3_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_lvds_sditf>;
};
};
};
&rkisp_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
};
};
};
&rkisp_vir2 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir2: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_lvds_sditf>;
};
};
};

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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3576-evb1.dtsi"
#include "rk3576-evb1-cam-3x.dtsi"
#include "rk3576-linux.dtsi"
/ {
model = "Rockchip RK3576 EVB1 V10 Board";
compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
};