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drm/rockchip: dsi2: sys_clk and pixel_clk should not be zero

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Change-Id: I8a92a1d12093b3562566349707c7ee0308e7d01c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2023-11-07 07:41:12 +00:00
committed by Tao Huang
parent f16cdb0b9b
commit ec130295af
1 changed files with 3 additions and 0 deletions
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drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
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@@ -629,6 +629,9 @@ static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
ipi_clk = pixel_clk / 4;
if (!sys_clk || !ipi_clk)
return;
tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
PHY_IPI_RATIO(tmp));