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phy: rockchip: mipi-dcphy: fix HSTX_CLK_SEL config

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set HSTX_CLK_SEL 1`b1 when cphy lane rate under 500Msps,
while set HSTX_CLK_SEL 1`b1 when dphy lane rate under 1500Mbps

Change-Id: Ic42ce385c1952febe0327594231f6bffb2543c5e
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2023-07-19 01:41:08 +00:00
committed by Tao Huang
parent 01edaa491a
commit ec50666d21
1 changed files with 2 additions and 2 deletions
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4
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
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@@ -1466,9 +1466,9 @@ static void samsung_mipi_cphy_timing_init(struct samsung_mipi_dcphy *samsung)
/*
* Divide-by-2 Clock from Serial Clock. Use this when data rate is under
* 1500Mbps, otherwise divide-by-16 Clock from Serial Clock
* 500Msps, otherwise divide-by-16 Clock from Serial Clock
*/
if (lane_hs_rate < 1500)
if (lane_hs_rate < 500)
val = HSTX_CLK_SEL;
val |= T_LPX(timing->lpx);