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arm64: dts: rockchip: Add RK3562 test1 and test2 board devicetree
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I1884bb4385a739b212f924f9996fe250ca0e8ffd
This commit is contained in:
@@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb
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9
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts
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9
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dts
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@@ -0,0 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3562-test1-ddr3-v10.dtsi"
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#include "rk3562-android.dtsi"
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#include "rk3562-rk809.dtsi"
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209
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
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209
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
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@@ -0,0 +1,209 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3562.dtsi"
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#include "rk3562-evb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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model = "Rockchip RK3562 TEST1 DDR3 V10 Board";
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compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562";
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_usb: vcc5v0-usb {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_usb_host: vcc5v0-usb-host {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb_host";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_usb>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb_host_pwren>;
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};
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vcc5v0_usb_otg: vcc5v0-usb-otg {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb_otg";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_usb>;
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pinctrl-names = "default";
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pinctrl-0 = <&usb_otg_pwren>;
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};
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vcc3v3_sys: vcc-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vcc25_ddr: vcc25-ddr {
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compatible = "regulator-fixed";
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regulator-name = "vcc25_ddr";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vdd_npu: vdd-npu {
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compatible = "pwm-regulator";
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pwms = <&pwm6 0 5000 1>;
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regulator-name = "vdd_npu";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1100000>;
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regulator-init-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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status = "okay";
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};
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};
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&combphy_pu {
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status = "okay";
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};
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&gmac0 {
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/* Use rgmii-rxid mode to disable rx delay inside Soc */
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phy-mode = "rgmii-rxid";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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tx_delay = <0x3f>;
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/* rx_delay = <0x3f>; */
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pinctrl-names = "default";
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pinctrl-0 = <&rgmiim1_miim
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&rgmiim1_tx_bus2
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&rgmiim1_rx_bus2
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&rgmiim1_rgmii_clk
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&rgmiim1_rgmii_bus
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ðm1_pins>;
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phy-handle = <&rgmii_phy>;
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status = "okay";
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};
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&mdio0 {
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rgmii_phy: phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
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assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>;
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assigned-clock-rates = <25000000>;
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};
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};
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&pinctrl {
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usb {
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usb_host_pwren: usb-host-pwren {
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rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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usb_otg_pwren: usb-otg-pwren {
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rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&sdmmc1 {
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no-sdio;
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no-mmc;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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disable-wp;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc3v3_sd>;
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vqmmc-supply = <&vccio_sd>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd &sdmmc1_det>;
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/* Should disable gmac0 and fix hardware if enabling sdmmc1 */
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status = "disabled";
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};
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&pwm6 {
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status = "okay";
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};
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&u2phy {
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status = "okay";
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};
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&u2phy_host {
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status = "okay";
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phy-supply = <&vcc5v0_usb_host>;
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};
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&u2phy_otg {
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status = "okay";
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vbus-supply = <&vcc5v0_usb_otg>;
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&usbdrd30 {
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status = "okay";
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};
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&usbdrd_dwc3 {
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status = "okay";
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dr_mode = "otg";
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extcon = <&u2phy>;
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};
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9
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts
Normal file
9
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dts
Normal file
@@ -0,0 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3562-test2-ddr4-v10.dtsi"
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#include "rk3562-android.dtsi"
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#include "rk3562-rk809.dtsi"
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91
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi
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91
arch/arm64/boot/dts/rockchip/rk3562-test2-ddr4-v10.dtsi
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@@ -0,0 +1,91 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3562.dtsi"
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#include "rk3562-evb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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model = "Rockchip RK3562 TEST2 DDR4 V10 Board";
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compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562";
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc3v3_sys: vcc-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vdd_npu: vdd-npu {
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compatible = "pwm-regulator";
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pwms = <&pwm6 0 5000 1>;
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regulator-name = "vdd_npu";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1100000>;
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regulator-init-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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status = "okay";
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};
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};
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&gmac0 {
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/* Use rgmii-rxid mode to disable rx delay inside Soc */
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phy-mode = "rmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmiim0_miim
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&rgmiim0_tx_bus2
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&rgmiim0_rx_bus2
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&rgmiim0_clk>;
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phy-handle = <&rmii_phy>;
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status = "okay";
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};
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&mdio0 {
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rmii_phy: phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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};
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};
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&pwm6 {
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status = "okay";
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};
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