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hdmitx: update hdmitx driver

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PD#154260: hdmitx: update hdmitx driver

1. using pr_info or pr_debug instead of printk.
2. remove unuse code.
3. change modulepara to sysfs.
4. use iomap api for read and write reg

Change-Id: I523329d7b26cd7c6675bdae55cda76a6a11c533e
Signed-off-by: Kaifu Hu <kaifu.hu@amlogic.com>
This commit is contained in:
Kaifu Hu
2017-12-21 16:18:45 +08:00
committed by Jianxin Pan
parent 72dcf27ab5
commit ee21b12b23
37 changed files with 1548 additions and 1545 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@@ -13500,6 +13500,7 @@ F: drivers/amlogic/power/*
HDMITX OUTPUT DRIVER
M: Zongdong Jiao <zongdong.jiao@amlogic.com>
M: Yi Zhou <yi.zhou@amlogic.com>
M: Kaifu Hu <kaifu.hu@amlogic.com>
S: Maintained
F: drivers/amlogic/media/vout/hdmitx/*
F: drivers/amlogic/media/vout/hdmitx/hdcp/*

4
arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts
View File

@@ -615,6 +615,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p212_1g_buildroot.dts
View File

@@ -603,6 +603,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts
View File

@@ -712,6 +712,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p212_2g_buildroot.dts
View File

@@ -680,6 +680,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p230_2g.dts
View File

@@ -701,6 +701,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p230_2g_buildroot.dts
View File

@@ -687,6 +687,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p231_1g.dts
View File

@@ -628,6 +628,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p231_2g.dts
View File

@@ -628,6 +628,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p231_2g_buildroot.dts
View File

@@ -620,6 +620,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p241_1g.dts
View File

@@ -687,6 +687,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p241_1g_buildroot.dts
View File

@@ -693,6 +693,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts
View File

@@ -664,6 +664,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

4
arch/arm64/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts
View File

@@ -662,6 +662,10 @@
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
/* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
* 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
*/
ic_type = <3>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */

30
drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
View File

@@ -1409,7 +1409,7 @@ struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t)
if (!t)
return NULL;
for (i = 0; all_fmt_paras[i]; i++) {
if ((abs(all_fmt_paras[i]->timing.frac_freq / 10
if ((abs(all_fmt_paras[i]->timing.pixel_freq / 10
- t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) &&
(t->h_active == all_fmt_paras[i]->timing.h_active) &&
(t->h_blank == all_fmt_paras[i]->timing.h_blank) &&
@@ -1584,20 +1584,22 @@ struct vinfo_s *hdmi_get_valid_vinfo(char *mode)
struct vinfo_s *info = NULL;
char mode_[32];
/* the string of mode contains char NF */
memset(mode_, 0, sizeof(mode_));
strncpy(mode_, mode, strlen(mode));
for (i = 0; i < sizeof(mode_); i++)
if (mode_[i] == 10)
mode_[i] = 0;
if (strlen(mode)) {
/* the string of mode contains char NF */
memset(mode_, 0, sizeof(mode_));
strncpy(mode_, mode, sizeof(mode_));
for (i = 0; i < sizeof(mode_); i++)
if (mode_[i] == 10)
mode_[i] = 0;
for (i = 0; all_fmt_paras[i]; i++) {
if (all_fmt_paras[i]->hdmitx_vinfo.mode == VMODE_MAX)
continue;
if (strncmp(all_fmt_paras[i]->hdmitx_vinfo.name, mode_,
strlen(mode_)) == 0) {
info = &all_fmt_paras[i]->hdmitx_vinfo;
break;
for (i = 0; all_fmt_paras[i]; i++) {
if (all_fmt_paras[i]->hdmitx_vinfo.mode == VMODE_MAX)
continue;
if (strncmp(all_fmt_paras[i]->hdmitx_vinfo.name, mode_,
strlen(mode_)) == 0) {
info = &all_fmt_paras[i]->hdmitx_vinfo;
break;
}
}
}
return info;

37
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_audio.c
View File

@@ -32,6 +32,8 @@
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h>
#include "hw/common.h"
#undef PCM_USE_INFOFRAME
@@ -53,17 +55,13 @@ static const unsigned char channel_status_sample_word_length[] = {
0xb /*24 bits*/
};
void hdmi_tx_set_N_CTS(unsigned int N_value, unsigned int CTS)
{
}
static void hdmi_tx_construct_aud_packet(
struct hdmitx_audpara *audio_param, unsigned char *AUD_DB,
unsigned char *CHAN_STAT_BUF, int hdmi_ch)
{
#ifndef PCM_USE_INFOFRAME
if (audio_param->type == CT_PCM) {
hdmi_print(INF, AUD "Audio Type: PCM\n");
pr_info(AUD "Audio Type: PCM\n");
if (AUD_DB) {
/*Note: HDMI Spec V1.4 Page 154*/
if ((audio_param->channel_num == CC_2CH) ||
@@ -97,7 +95,7 @@ static void hdmi_tx_construct_aud_packet(
audio_param->sample_rate])<<4);
}
} else if (audio_param->type == CT_AC_3) {
hdmi_print(INF, AUD "Audio Type: AC3\n");
pr_info(AUD "Audio Type: AC3\n");
if (AUD_DB) {
AUD_DB[0] = (CT_AC_3<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -105,7 +103,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MPEG1) {
hdmi_print(INF, AUD "Audio Type: MPEG1\n");
pr_info(AUD "Audio Type: MPEG1\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MPEG1<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -113,7 +111,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MP3) {
hdmi_print(INF, AUD "Audio Type: MP3\n");
pr_info(AUD "Audio Type: MP3\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MP3<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -121,7 +119,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MPEG2) {
hdmi_print(INF, AUD "Audio Type: MPEG2\n");
pr_info(AUD "Audio Type: MPEG2\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MPEG2<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -129,7 +127,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_AAC) {
hdmi_print(INF, AUD "Audio Type: AAC\n");
pr_info(AUD "Audio Type: AAC\n");
if (AUD_DB) {
AUD_DB[0] = (CT_AAC<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -137,7 +135,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DTS) {
hdmi_print(INF, AUD "Audio Type: DTS\n");
pr_info(AUD "Audio Type: DTS\n");
if (AUD_DB) {
AUD_DB[0] = (CT_DTS<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -145,7 +143,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_ATRAC) {
hdmi_print(INF, AUD "Audio Type: ATRAC\n");
pr_info(AUD "Audio Type: ATRAC\n");
if (AUD_DB) {
AUD_DB[0] = (CT_ATRAC<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -153,7 +151,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_ONE_BIT_AUDIO) {
hdmi_print(INF, AUD "Audio Type: One Bit Audio\n");
pr_info(AUD "Audio Type: One Bit Audio\n");
if (AUD_DB) {
AUD_DB[0] = (CT_ONE_BIT_AUDIO<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -161,7 +159,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DOLBY_D) {
hdmi_print(INF, AUD "Audio Type: Dobly Digital +\n");
pr_info(AUD "Audio Type: Dobly Digital +\n");
if (AUD_DB) {
AUD_DB[0] =
(FS_REFER_TO_STREAM<<4)|(CC_REFER_TO_STREAM);
@@ -175,7 +173,7 @@ static void hdmi_tx_construct_aud_packet(
CHAN_STAT_BUF[4] = CHAN_STAT_BUF[24+4] = 0x1;
}
} else if (audio_param->type == CT_DTS_HD) {
hdmi_print(INF, AUD "Audio Type: DTS-HD\n");
pr_info(AUD "Audio Type: DTS-HD\n");
if (AUD_DB) {
AUD_DB[0] =
(FS_REFER_TO_STREAM<<4)|(CC_REFER_TO_STREAM);
@@ -184,7 +182,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_MAT) {
hdmi_print(INF, AUD "Audio Type: MAT(MLP)\n");
pr_info(AUD "Audio Type: MAT(MLP)\n");
if (AUD_DB) {
AUD_DB[0] = (CT_MAT<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -192,7 +190,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_DST) {
hdmi_print(INF, AUD "Audio Type: DST\n");
pr_info(AUD "Audio Type: DST\n");
if (AUD_DB) {
AUD_DB[0] = (CT_DST<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -200,7 +198,7 @@ static void hdmi_tx_construct_aud_packet(
AUD_DB[4] = 0;
}
} else if (audio_param->type == CT_WMA) {
hdmi_print(INF, AUD "Audio Type: WMA Pro\n");
pr_info(AUD "Audio Type: WMA Pro\n");
if (AUD_DB) {
AUD_DB[0] = (CT_WMA<<4)|(CC_REFER_TO_STREAM);
AUD_DB[1] = (FS_REFER_TO_STREAM<<2)|SS_REFER_TO_STREAM;
@@ -218,11 +216,12 @@ static void hdmi_tx_construct_aud_packet(
}
int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
struct hdmitx_audpara *audio_param, int hdmi_ch)
struct hdmitx_audpara *audio_param)
{
int i, ret = -1;
unsigned char AUD_DB[32];
unsigned char CHAN_STAT_BUF[24*2];
unsigned int hdmi_ch = hdmitx_device->hdmi_ch;
for (i = 0; i < 32; i++)
AUD_DB[i] = 0;

95
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
View File

@@ -29,18 +29,16 @@
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/uaccess.h>
/* #include <mach/register.h> */
/* #include <plat/io.h> */
/* #include "hw/hdmi_tx_reg.h" */
#include <crypto/hash.h>
#include <linux/crypto.h>
#include <linux/scatterlist.h>
/* #include <mach/am_regs.h> */
#include <linux/delay.h>
#include <linux/amlogic/media/vout/vinfo.h>
#include <linux/amlogic/media/vout/vout_notify.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "hw/common.h"
#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04
#define VIDEO_TAG 0x40
@@ -151,11 +149,9 @@ static void Edid_ParsingIDSerialNumber(struct rx_cap *pRXCap,
{
int i;
if (data == NULL)
return;
for (i = 0; i < 4; i++)
pRXCap->IDSerialNumber[i] = data[3-i];
return;
if (data != NULL)
for (i = 0; i < 4; i++)
pRXCap->IDSerialNumber[i] = data[3-i];
}
static int Edid_find_name_block(unsigned char *data)
@@ -243,6 +239,7 @@ static void set_vsdb_phy_addr(struct hdmitx_dev *hdev,
unsigned char *edid_offset)
{
int phy_addr;
vsdb->a = (edid_offset[4] >> 4) & 0xf;
vsdb->b = (edid_offset[4] >> 0) & 0xf;
vsdb->c = (edid_offset[5] >> 4) & 0xf;
@@ -777,11 +774,10 @@ static void Edid_ParsingVendSpec(struct rx_cap *pRXCap,
pos++;
if (dat[pos] != 1) {
pr_info("hdmitx: edid: parsing fail %s[%d]\n", __func__,
pr_info(EDID "parsing fail %s[%d]\n", __func__,
__LINE__);
return;
} else
pos++;
} else {
pos++;
dv->ieeeoui = dat[pos++];
dv->ieeeoui += dat[pos++] << 8;
@@ -842,6 +838,8 @@ static void Edid_ParsingVendSpec(struct rx_cap *pRXCap,
dv->vers.ver1.chrom_blue_primary_x = dat[pos++];
dv->vers.ver1.chrom_blue_primary_y = dat[pos++];
}
}
if (pos > len)
pr_info("hdmitx: edid: maybe invalid dv%d data\n", dv->ver);
}
@@ -1238,8 +1236,8 @@ static void hdmitx_edid_4k2k_parse(struct rx_cap *pRXCap, unsigned char *dat,
unsigned int size)
{
if ((size > 4) || (size == 0)) {
hdmi_print(ERR, EDID
"HDMI: 4k2k in edid out of range, SIZE = %d\n",
pr_info(EDID
"4k2k in edid out of range, SIZE = %d\n",
size);
return;
}
@@ -1483,7 +1481,7 @@ static void hdmitx_edid_set_default_vic(struct hdmitx_dev *hdmitx_device)
pRXCap->VIC[2] = HDMI_1920x1080p60_16x9;
pRXCap->native_VIC = HDMI_720x480p60_16x9;
hdmitx_device->vic_count = pRXCap->VIC_count;
hdmi_print(IMP, EDID "HDMI: set default vic\n");
pr_info(EDID "set default vic\n");
}
#if 0
@@ -1705,8 +1703,8 @@ static int edid_zero_data(unsigned char *buf)
static void dump_dtd_info(struct dtd *t)
{
pr_info("%s[%d]\n", __func__, __LINE__);
#define PR(a) pr_info("%s %d\n", #a, t->a)
pr_info(EDID "%s[%d]\n", __func__, __LINE__);
#define PR(a) pr_info(EDID "%s: %d\n", #a, t->a)
PR(pixel_clock);
PR(h_active);
PR(h_blank);
@@ -1761,7 +1759,7 @@ next:
if (para) {
t->vic = para->vic;
pRXCap->preferred_mode = pRXCap->dtd[0].vic; /* Select dtd0 */
pr_info("hdmitx: get dtd%d vic: %d\n",
pr_info(EDID "get dtd%d vic: %d\n",
pRXCap->dtd_idx, para->vic);
pRXCap->dtd_idx++;
} else
@@ -1787,7 +1785,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
} else
EDID_buf = hdmitx_device->EDID_buf1;
hdmitx_device->edid_ptr = EDID_buf;
hdmi_print(0, "EDID Parser:\n");
pr_info(EDID "EDID Parser:\n");
memset(rptx_edid_buf, 0, sizeof(rptx_edid_buf));
rptx_edid_aud = &rptx_edid_buf[0];
/* Calculate the EDID hash for special use */
@@ -1797,18 +1795,13 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
ret_val = Edid_DecodeHeader(&hdmitx_device->hdmi_info, &EDID_buf[0]);
/* if(ret_val == -1) */
/* return -1; */
for (i = 0, CheckSum = 0 ; i < 128 ; i++) {
CheckSum += EDID_buf[i];
CheckSum &= 0xFF;
}
if (CheckSum != 0) {
hdmi_print(0, "PLUGIN_DVI_OUT\n");
/* return -1 ; */
}
if (CheckSum != 0)
pr_info(EDID "PLUGIN_DVI_OUT\n");
Edid_ParsingIDManufacturerName(&hdmitx_device->RXCap, &EDID_buf[8]);
Edid_ParsingIDProductCode(&hdmitx_device->RXCap, &EDID_buf[0x0A]);
@@ -1840,7 +1833,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
hdmitx_device->RXCap.blk0_chksum = EDID_buf[0x7F];
if (BlockCount == 0) {
hdmi_print(0, "EDID BlockCount=0\n");
pr_info(EDID "EDID BlockCount=0\n");
hdmitx_edid_set_default_vic(hdmitx_device);
/* DVI case judgement: only contains one block and
@@ -1853,7 +1846,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
if (EDID_buf[i] == 0)
zero_numbers++;
}
hdmi_print(INF, EDID "edid blk0 checksum:%d ext_flag:%d\n",
pr_info(EDID "edid blk0 checksum:%d ext_flag:%d\n",
CheckSum, EDID_buf[0x7e]);
if ((CheckSum & 0xff) == 0)
hdmitx_device->RXCap.IEEEOUI = 0;
@@ -1874,7 +1867,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
hdmitx_device->RXCap.VIC[2] = HDMI_1920x1080p60_16x9;
hdmitx_device->RXCap.native_VIC = HDMI_720x480p60_16x9;
hdmitx_device->vic_count = hdmitx_device->RXCap.VIC_count;
hdmi_print(IMP, EDID "HDMI: set default vic\n");
pr_info(EDID "set default vic\n");
return 0;
} else if (BlockCount > EDID_MAX_BLOCK) {
BlockCount = EDID_MAX_BLOCK;
@@ -1921,17 +1914,17 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
*/
if (!pRXCap->flag_vfpdb && (pRXCap->preferred_mode != pRXCap->VIC[0]) &&
(pRXCap->number_of_dtd == 0)) {
pr_info("hdmitx: edid: change preferred_mode from %d to %d\n",
pr_info(EDID "change preferred_mode from %d to %d\n",
pRXCap->preferred_mode, pRXCap->VIC[0]);
pRXCap->preferred_mode = pRXCap->VIC[0];
}
if (hdmitx_edid_search_IEEEOUI(&EDID_buf[128])) {
pRXCap->IEEEOUI = 0x0c03;
pr_info("hdmitx: edid: find IEEEOUT\n");
pr_info(EDID "find IEEEOUT\n");
} else {
pRXCap->IEEEOUI = 0x0;
pr_info("hdmitx: edid: not find IEEEOUT\n");
pr_info(EDID "not find IEEEOUT\n");
}
if ((pRXCap->IEEEOUI != 0x0c03) || (pRXCap->IEEEOUI == 0x0) ||
@@ -1943,7 +1936,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
if (edid_check_valid(&EDID_buf[0]) &&
!hdmitx_edid_search_IEEEOUI(&EDID_buf[128])) {
pRXCap->IEEEOUI = 0x0;
pr_info("hdmitx: edid: sink is DVI device\n");
pr_info(EDID "sink is DVI device\n");
} else
pRXCap->IEEEOUI = 0x0c03;
@@ -1955,15 +1948,13 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
edid_save_checkvalue(EDID_buf, BlockCount+1);
#if 1
i = hdmitx_edid_dump(hdmitx_device, (char *)(hdmitx_device->tmp_buf),
HDMI_TMP_BUF_SIZE);
hdmitx_device->tmp_buf[i] = 0;
hdmi_print(0, "\n");
#endif
if (!hdmitx_edid_check_valid_blocks(&EDID_buf[0])) {
pRXCap->IEEEOUI = 0x0c03;
pr_info("hdmitx: Invalid edid, consider RX as HDMI device\n");
pr_info(EDID "Invalid edid, consider RX as HDMI device\n");
}
/* update RX HDR information */
info = get_current_vinfo();
@@ -1979,7 +1970,7 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device)
info->hdr_info.lumi_max = pRXCap->hdr_lum_max;
info->hdr_info.lumi_avg = pRXCap->hdr_lum_avg;
info->hdr_info.lumi_min = pRXCap->hdr_lum_min;
pr_info("hdmitx: update rx hdr info %x at edid parsing\n",
pr_info(EDID "update rx hdr info %x at edid parsing\n",
info->hdr_info.hdr_support);
}
}
@@ -2007,14 +1998,15 @@ static struct dispmode_vic dispmode_vic_tab[] = {
{"smpte24hz", HDMI_4k2k_smpte_24},
{"smpte25hz", HDMI_4096x2160p25_256x135},
{"smpte30hz", HDMI_4096x2160p30_256x135},
{"smpte50hz", HDMI_4096x2160p50_256x135},
{"smpte50hz420", HDMI_4096x2160p50_256x135_Y420},
{"smpte60hz", HDMI_4096x2160p60_256x135},
{"smpte60hz420", HDMI_4096x2160p60_256x135_Y420},
{"2160p60hz", HDMI_4k2k_60},
{"2160p50hz", HDMI_4k2k_50},
{"2160p60hz420", HDMI_3840x2160p60_16x9_Y420},
{"2160p50hz420", HDMI_3840x2160p50_16x9_Y420},
{"smpte50hz", HDMI_4096x2160p50_256x135},
{"smpte60hz", HDMI_4096x2160p60_256x135},
{"2160p60hz", HDMI_4k2k_60},
{"2160p50hz", HDMI_4k2k_50},
};
int hdmitx_edid_VIC_support(enum hdmi_vic vic)
@@ -2035,14 +2027,15 @@ enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode)
int i;
for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) {
if (strcmp(disp_mode, dispmode_vic_tab[i].disp_mode) == 0) {
if (strncmp(disp_mode, dispmode_vic_tab[i].disp_mode,
strlen(dispmode_vic_tab[i].disp_mode)) == 0) {
vic = dispmode_vic_tab[i].VIC;
break;
}
}
if (vic == HDMI_Unknown)
hdmi_print(INF, EDID "not find mapped vic\n");
pr_info(EDID "not find mapped vic\n");
return vic;
}
@@ -2332,14 +2325,14 @@ static void hdmitx_edid_blk_print(unsigned char *blk, unsigned int blk_idx)
return;
memset(tmp_buf, 0, TMP_EDID_BUF_SIZE);
hdmi_print(INF, EDID "blk%d raw data\n", blk_idx);
pr_info(EDID "blk%d raw data\n", blk_idx);
for (i = 0, pos = 0; i < 128; i++) {
pos += sprintf(tmp_buf + pos, "%02x", blk[i]);
if (((i+1) & 0x1f) == 0) /* print 32bytes a line */
pos += sprintf(tmp_buf + pos, "\n");
}
pos += sprintf(tmp_buf + pos, "\n");
pr_info("%s\n", tmp_buf);
pr_info(EDID "\n%s\n", tmp_buf);
kfree(tmp_buf);
}
@@ -2358,9 +2351,9 @@ static unsigned int hdmitx_edid_check_valid_blocks(unsigned char *buf)
if (tmp_chksum != 0) {
valid_blk_no++;
if ((tmp_chksum & 0xff) == 0)
hdmi_print(INF, EDID "check sum valid\n");
pr_info(EDID "check sum valid\n");
else
hdmi_print(INF, EDID "check sum invalid\n");
pr_info(EDID "check sum invalid\n");
}
tmp_chksum = 0;
}
@@ -2391,14 +2384,14 @@ void hdmitx_edid_buf_compare_print(struct hdmitx_dev *hdmitx_device)
valid_blk_no = hdmitx_edid_check_valid_blocks(buf0);
if (valid_blk_no == 0)
hdmi_print(ERR, EDID "raw data are all zeroes\n");
pr_info(EDID "raw data are all zeroes\n");
else {
for (blk_idx = 0; blk_idx < valid_blk_no; blk_idx++)
hdmitx_edid_blk_print(&buf0[blk_idx*128],
blk_idx);
}
} else {
hdmi_print(ERR, EDID "%d errors between two reading\n", err_no);
pr_info(EDID "%d errors between two reading\n", err_no);
valid_blk_no = hdmitx_edid_check_valid_blocks(buf0);
for (blk_idx = 0; blk_idx < valid_blk_no; blk_idx++)
hdmitx_edid_blk_print(&buf0[blk_idx*128], blk_idx);

24
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.c
View File

@@ -42,7 +42,7 @@
/* #include <mach/am_regs.h> */
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
/* #include <mach/hdmi_tx_reg.h> */
#include "hw/common.h"
#include "hdmi_tx_hdcp.h"
/*
* hdmi_tx_hdcp.c
@@ -52,6 +52,24 @@
static int hdmi_authenticated;
unsigned int hdcp_get_downstream_ver(void)
{
unsigned int ret = 14;
struct hdmitx_dev *hdev = get_hdmitx_device();
/* if TX don't have HDCP22 key, skip RX hdcp22 ver */
if (hdev->HWOp.CntlDDC(hdev,
DDC_HDCP_22_LSTORE, 0) == 0)
if (hdcp_rd_hdcp22_ver())
ret = 22;
else
ret = 14;
else
ret = 14;
return ret;
}
/* Notic: the HDCP key setting has been moved to uboot
* On MBX project, it is too late for HDCP get from
* other devices
@@ -107,9 +125,9 @@ static int __init hdmitx_hdcp_init(void)
{
struct hdmitx_dev *hdev = get_hdmitx_device();
pr_info("hdmitx_hdcp_init\n");
pr_info(HDCP "hdmitx_hdcp_init\n");
if (hdev->hdtx_dev == NULL) {
hdmi_print(IMP, SYS "exit for null device of hdmitx!\n");
pr_info(HDCP "exit for null device of hdmitx!\n");
return -ENODEV;
}

6
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h
View File

@@ -26,10 +26,8 @@
* On MBX project, it is too late for HDCP get from
* other devices
*/
/* int task_tx_key_setting(unsigned force_wrong); */
int hdcp_ksv_valid(unsigned char *dat);
extern int hdcp_ksv_valid(unsigned char *dat);
extern unsigned int hdcp_get_downstream_ver(void);
#endif

1027
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_scdc.c
View File

@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
#include "hw/common.h"
static struct timer_list scdc_tmds_cfg_timer;

103
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c
View File

@@ -32,8 +32,8 @@
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_compliance.h>
#include "hw/common.h"
static unsigned char hdmi_output_rgb;
static void hdmitx_set_spd_info(struct hdmitx_dev *hdmitx_device);
static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdmitx_device,
enum hdmi_vic VideoCode);
@@ -551,25 +551,6 @@ static void hdmi_tx_construct_avi_packet(
* hdmitx protocol level interface
*************************************/
void hdmitx_init_parameters(struct hdmitx_info *info)
{
memset(info, 0, sizeof(struct hdmitx_info));
info->video_out_changing_flag = 1;
info->audio_flag = 1;
info->audio_info.type = CT_REFER_TO_STREAM;
info->audio_info.format = AF_I2S;
info->audio_info.fs = FS_44K1;
info->audio_info.ss = SS_16BITS;
info->audio_info.channels = CC_2CH;
info->audio_out_changing_flag = 1;
info->auto_hdcp_ri_flag = 1;
info->hw_sha_calculator_flag = 1;
}
/*
* HDMI Identifier = 0x000c03
* If not, treated as a DVI Device
@@ -582,11 +563,6 @@ static int is_dvi_device(struct rx_cap *pRXCap)
return 0;
}
void hdmitx_output_rgb(void)
{
hdmi_output_rgb = 1;
}
int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
{
struct hdmitx_vidpara *param = NULL;
@@ -602,51 +578,46 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
AVI_DB[i] = 0;
vic = hdev->HWOp.GetState(hdev, STAT_VIDEO_VIC, 0);
hdmi_print(IMP, SYS "already init VIC = %d Now VIC = %d\n",
pr_info(VID "already init VIC = %d Now VIC = %d\n",
vic, VideoCode);
if ((vic != HDMI_Unknown) && (vic == VideoCode)) {
if ((vic != HDMI_Unknown) && (vic == VideoCode))
hdev->cur_VIC = vic;
/* return 1; */
}
param = hdmi_get_video_param(VideoCode);
hdev->cur_video_param = param;
if (param) {
param->color = param->color_prefer;
if (hdmi_output_rgb) {
/* HDMI CT 7-24 Pixel Encoding
* YCbCr to YCbCr Sink
*/
switch (hdev->RXCap.native_Mode & 0x30) {
case 0x20:/*bit5==1, then support YCBCR444 + RGB*/
case 0x30:
param->color = COLORSPACE_YUV444;
break;
case 0x10:/*bit4==1, then support YCBCR422 + RGB*/
param->color = COLORSPACE_YUV422;
break;
default:
param->color = COLORSPACE_RGB444;
} else {
/* HDMI CT 7-24 Pixel Encoding
* YCbCr to YCbCr Sink
*/
switch (hdev->RXCap.native_Mode & 0x30) {
case 0x20:/*bit5==1, then support YCBCR444 + RGB*/
case 0x30:
param->color = COLORSPACE_YUV444;
break;
case 0x10:/*bit4==1, then support YCBCR422 + RGB*/
param->color = COLORSPACE_YUV422;
break;
default:
param->color = COLORSPACE_RGB444;
}
/* For Y420 modes */
switch (VideoCode) {
case HDMI_3840x2160p50_16x9_Y420:
case HDMI_3840x2160p60_16x9_Y420:
case HDMI_4096x2160p50_256x135_Y420:
case HDMI_4096x2160p60_256x135_Y420:
param->color = COLORSPACE_YUV420;
break;
default:
break;
}
if (param->color == COLORSPACE_RGB444) {
hdev->para->cs = hdev->cur_video_param->color;
pr_info("hdmitx: rx edid only support RGB format\n");
}
}
/* For Y420 modes */
switch (VideoCode) {
case HDMI_3840x2160p50_16x9_Y420:
case HDMI_3840x2160p60_16x9_Y420:
case HDMI_4096x2160p50_256x135_Y420:
case HDMI_4096x2160p60_256x135_Y420:
param->color = COLORSPACE_YUV420;
break;
default:
break;
}
if (param->color == COLORSPACE_RGB444) {
hdev->para->cs = hdev->cur_video_param->color;
pr_info(VID "rx edid only support RGB format\n");
}
if (hdev->HWOp.SetDispMode(hdev) >= 0) {
/* HDMI CT 7-33 DVI Sink, no HDMI VSDB nor any
* other VSDB, No GB or DI expected
@@ -654,11 +625,11 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
* 0: DVI Mode 1: HDMI Mode
*/
if (is_dvi_device(&hdev->RXCap)) {
hdmi_print(1, "Sink is DVI device\n");
pr_info(VID "Sink is DVI device\n");
hdev->HWOp.CntlConfig(hdev,
CONF_HDMI_DVI_MODE, DVI_MODE);
} else {
hdmi_print(1, "Sink is HDMI device\n");
pr_info(VID "Sink is HDMI device\n");
hdev->HWOp.CntlConfig(hdev,
CONF_HDMI_DVI_MODE, HDMI_MODE);
}
@@ -678,9 +649,7 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode)
}
}
hdmitx_set_spd_info(hdev);
#if 0
hdmitx_special_handler_video(hdev);
#endif
return ret;
}
@@ -756,7 +725,7 @@ static void hdmitx_set_spd_info(struct hdmitx_dev *hdev)
if (hdev->config_data.vend_data)
vend_data = hdev->config_data.vend_data;
else {
hdmi_print(INF, SYS "packet: can\'t get vendor data\n");
pr_info(VID "packet: can\'t get vendor data\n");
return;
}
if (vend_data->vendor_name) {

23
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/common.h
View File

@@ -20,8 +20,27 @@
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_common.h>
#include "mach_reg.h"
#include "hdmi_tx_reg.h"
/***********************************************************************
* hdmi debug printk
* pr_info(EDID "edid bad\");
* pr_debug(AUD "set audio format: AC-3\n");
* pr_err(REG "write reg\n")
**********************************************************************/
#undef pr_fmt
#define pr_fmt(fmt) "hdmitx: " fmt
#define VID "video: "
#define AUD "audio: "
#define CEC "cec: "
#define EDID "edid: "
#define HDCP "hdcp: "
#define SYS "system: "
#define HPD "hpd: "
#define HW "hw: "
#define REG "reg: "
/*
* HDMITX HPD HW related operations
*/
@@ -54,5 +73,7 @@ void set_hpll_od3_gxl(unsigned int div);
int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd);
int read_hpd_gpio_txlx(void);
int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd);
extern unsigned int hdmitx_get_format_txlx(void);
extern void hdmitx_sys_reset_txlx(void);
#endif

67
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
View File

@@ -37,6 +37,7 @@
#include <linux/amlogic/media/vout/hdmi_tx/enc_clk_config.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "common.h"
#include "mach_reg.h"
#define MREG_END_MARKER 0xFFFF
@@ -744,37 +745,6 @@ static struct vic_tvregs_set tvregsTab[] = {
{HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz},
};
static inline void setreg(const struct reg_s *r)
{
hd_write_reg(r->reg, r->val);
/* printk("[0x%x] = 0x%x\n", r->reg, r->val); */
}
static const struct reg_s *tvregs_setting_mode(enum hdmi_vic vic)
{
int i = 0;
for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) {
if (vic == tvregsTab[i].vic)
return tvregsTab[i].reg_setting;
}
return NULL;
}
void set_vmode_enc_hw(enum hdmi_vic vic)
{
const struct reg_s *s = tvregs_setting_mode(vic);
/* Turn off VDAC, no need any more for HDMITX */
hd_set_reg_bits(P_VENC_VDAC_SETTING, 0x1f, 0, 5);
if (s) {
pr_info("hdmitx: set enc for VIC: %d\n", vic);
while (s->reg != MREG_END_MARKER)
setreg(s++);
} else
pr_info("hdmitx: not find VIC: %d\n", vic);
}
/*
* For 3D FramePacket Setting
*/
@@ -989,25 +959,44 @@ static struct vic_tvregs_set tvregsTab_3dfp[] = {
{HDMI_1280x720p50_16x9, tvregs_3dfp_720p50},
};
static const struct reg_s *tvregs_3dfp_setting_mode(enum hdmi_vic vic)
static inline void setreg(const struct reg_s *r)
{
hd_write_reg(r->reg, r->val);
}
static const struct reg_s *tvregs_setting_mode(struct hdmitx_dev *hdev)
{
int i = 0;
enum hdmi_vic vic = hdev->cur_video_param->VIC;
for (i = 0; i < ARRAY_SIZE(tvregsTab_3dfp); i++) {
if (vic == tvregsTab_3dfp[i].vic)
return tvregsTab_3dfp[i].reg_setting;
if (hdev->flag_3dfp) {
for (i = 0; i < ARRAY_SIZE(tvregsTab_3dfp); i++) {
if (vic == tvregsTab_3dfp[i].vic)
return tvregsTab_3dfp[i].reg_setting;
}
} else {
for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) {
if (vic == tvregsTab[i].vic)
return tvregsTab[i].reg_setting;
}
}
return NULL;
}
void set_vmode_3dfp_enc_hw(enum hdmi_vic vic)
void set_vmode_enc_hw(struct hdmitx_dev *hdev)
{
const struct reg_s *s = tvregs_3dfp_setting_mode(vic);
const struct reg_s *s = tvregs_setting_mode(hdev);
/* Turn off VDAC, no need any more for HDMITX */
hd_set_reg_bits(P_VENC_VDAC_SETTING, 0x1f, 0, 5);
if (s) {
pr_info("hdmitx: set 3dfp enc for VIC: %d\n", vic);
pr_info("set enc for VIC: %d\n",
hdev->cur_video_param->VIC);
while (s->reg != MREG_END_MARKER)
setreg(s++);
} else
pr_info("hdmitx: not find VIC: %d\n", vic);
pr_info("set enc not find VIC: %d\n",
hdev->cur_video_param->VIC);
}

6
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_ddc.c
View File

@@ -37,7 +37,7 @@
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_ddc.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "common.h"
#include "hdmi_tx_reg.h"
static DEFINE_MUTEX(ddc_mutex);
@@ -54,7 +54,7 @@ static uint32_t ddc_write_1byte(uint8_t slave, uint8_t offset_addr,
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc w1b error 0x%02x 0x%02x 0x%02x\n",
pr_info("ddc w1b error 0x%02x 0x%02x 0x%02x\n",
slave, offset_addr, data);
} else
st = 1;
@@ -157,7 +157,7 @@ static uint32_t ddc_read_1byte(uint8_t slave, uint8_t offset_addr,
mdelay(2);
if (hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 0)) {
st = 0;
pr_info("hdmitx: ddc rd8b error 0x%02x 0x%02x\n",
pr_info("ddc rd8b error 0x%02x 0x%02x\n",
slave, offset_addr);
} else
st = 1;

833
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

File diff suppressed because it is too large Load Diff

32
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_reg.h
View File

@@ -906,22 +906,22 @@ int hdmitx_hdcp_opr(unsigned int val);
/* [ 0] ksv_mem_request */
#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016)
#define HDMITX_DWC_HDCP_BSTATUS_0 (DWC_OFFSET_MASK + 0x5020)
#define HDMITX_DWC_HDCP_BSTATUS_1 (DWC_OFFSET_MASK + 0x5021)
#define HDMITX_DWC_HDCP_M0_0 (DWC_OFFSET_MASK + 0x5022)
#define HDMITX_DWC_HDCP_M0_1 (DWC_OFFSET_MASK + 0x5023)
#define HDMITX_DWC_HDCP_M0_2 (DWC_OFFSET_MASK + 0x5024)
#define HDMITX_DWC_HDCP_M0_3 (DWC_OFFSET_MASK + 0x5025)
#define HDMITX_DWC_HDCP_M0_4 (DWC_OFFSET_MASK + 0x5026)
#define HDMITX_DWC_HDCP_M0_5 (DWC_OFFSET_MASK + 0x5027)
#define HDMITX_DWC_HDCP_M0_6 (DWC_OFFSET_MASK + 0x5028)
#define HDMITX_DWC_HDCP_M0_7 (DWC_OFFSET_MASK + 0x5029)
#define HDMITX_DWC_HDCP_KSV (DWC_OFFSET_MASK + 0x502A)
#define HDMITX_DWC_HDCP_VH (DWC_OFFSET_MASK + 0x52A5)
#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (DWC_OFFSET_MASK + 0x52B9)
#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (DWC_OFFSET_MASK + 0x52BA)
#define HDMITX_DWC_HDCP_REVOC_LIST (DWC_OFFSET_MASK + 0x52BB)
#define HDMITX_DWC_HDCP_REVOC_LIST_END (DWC_OFFSET_MASK + 0x667E)
#define HDMITX_DWC_HDCP_BSTATUS_0 (TOP_OFFSET_MASK + 0x2000)
#define HDMITX_DWC_HDCP_BSTATUS_1 (TOP_OFFSET_MASK + 0x2001)
#define HDMITX_DWC_HDCP_M0_0 (TOP_OFFSET_MASK + 0x2002)
#define HDMITX_DWC_HDCP_M0_1 (TOP_OFFSET_MASK + 0x2003)
#define HDMITX_DWC_HDCP_M0_2 (TOP_OFFSET_MASK + 0x2004)
#define HDMITX_DWC_HDCP_M0_3 (TOP_OFFSET_MASK + 0x2005)
#define HDMITX_DWC_HDCP_M0_4 (TOP_OFFSET_MASK + 0x2006)
#define HDMITX_DWC_HDCP_M0_5 (TOP_OFFSET_MASK + 0x2007)
#define HDMITX_DWC_HDCP_M0_6 (TOP_OFFSET_MASK + 0x2008)
#define HDMITX_DWC_HDCP_M0_7 (TOP_OFFSET_MASK + 0x2009)
#define HDMITX_DWC_HDCP_KSV (TOP_OFFSET_MASK + 0x200A)
#define HDMITX_DWC_HDCP_VH (TOP_OFFSET_MASK + 0x2285)
#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (TOP_OFFSET_MASK + 0x2299)
#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (TOP_OFFSET_MASK + 0x229A)
#define HDMITX_DWC_HDCP_REVOC_LIST (TOP_OFFSET_MASK + 0x229B)
#define HDMITX_DWC_HDCP_REVOC_LIST_END (TOP_OFFSET_MASK + 0x365E)
/* HDCP BKSV Registers */
#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800)

255
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -19,16 +19,11 @@
#include <linux/printk.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "common.h"
#include "mach_reg.h"
#include "hw_clk.h"
/* local frac_rate flag */
static uint32_t frac_rate;
/* enable or disable HDMITX SSPLL, enable by default */
static int sspll_en = 1;
/*
* HDMITX Clock configuration
*/
@@ -59,14 +54,92 @@ static inline int check_div(unsigned int div)
return div;
}
static void set_hdmitx_sys_clk(void)
void hdmitx_set_sys_clk(struct hdmitx_dev *hdev, unsigned char flag)
{
if (flag&4)
hdmitx_set_cts_sys_clk(hdev);
if (flag&2) {
hdmitx_set_top_pclk(hdev);
hdmitx_set_vclk2_encp(hdev);
}
}
void hdmitx_set_vclk2_encp(struct hdmitx_dev *hdev)
{
hd_write_reg(P_HHI_GCLK_OTHER,
hd_read_reg(P_HHI_GCLK_OTHER)|(1<<17));
}
void hdmitx_set_vclk2_enci(struct hdmitx_dev *hdev)
{
hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 8, 1);
}
void hdmitx_set_cts_sys_clk(struct hdmitx_dev *hdev)
{
/* Enable cts_hdmitx_sys_clk */
/* .clk0 ( cts_oscin_clk ), */
/* .clk1 ( fclk_div4 ), */
/* .clk2 ( fclk_div3 ), */
/* .clk3 ( fclk_div5 ), */
/* [10: 9] clk_sel. select cts_oscin_clk=24MHz */
/* [ 8] clk_en. Enable gated clock */
/* [ 6: 0] clk_div. Divide by 1. = 24/1 = 24 MHz */
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 0, 7);
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 1, 8, 1);
}
static void set_gxb_hpll_clk_out(unsigned int clk)
void hdmitx_set_top_pclk(struct hdmitx_dev *hdev)
{
/* top hdmitx pixel clock */
hd_write_reg(P_HHI_GCLK_MPEG2,
hd_read_reg(P_HHI_GCLK_MPEG2) | (1<<4));
}
void hdmitx_set_cts_hdcp22_clk(struct hdmitx_dev *hdev)
{
switch (hdev->chip_type) {
case MESON_CPU_ID_TXLX:
/* Enable cts_hdcp22_skpclk */
/* .clk0 ( cts_oscin_clk ), */
/* .clk1 ( fclk_div4 ), */
/* .clk2 ( fclk_div3 ), */
/* .clk3 ( fclk_div5 ), */
/* [26: 25] clk_sel. select cts_oscin_clk=24MHz */
/* [ 24] clk_en. Enable gated clock */
/* [22: 16] clk_div. Divide by 1. = 24/1 = 24 MHz */
clk_set_rate(hdev->hdmitx_clk_tree.hdcp22_tx_skp, 24000000);
clk_prepare_enable(hdev->hdmitx_clk_tree.hdcp22_tx_skp);
/* Enable cts_hdcp22_esmclk */
/* .clk0 ( fclk_div7 ), */
/* .clk1 ( fclk_div4 ), */
/* .clk2 ( fclk_div3 ), */
/* .clk3 ( fclk_div5 ), */
/* [10: 9] clk_sel. select fclk_div7*/
/* [ 8] clk_en. Enable gated clock */
/* [ 6: 0] clk_div. Divide by 1.*/
clk_set_rate(hdev->hdmitx_clk_tree.hdcp22_tx_esm, 285714285);
clk_prepare_enable(hdev->hdmitx_clk_tree.hdcp22_tx_esm);
break;
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
break;
}
}
void hdmitx_set_hdcp_pclk(struct hdmitx_dev *hdev)
{
/* top hdcp pixel clock */
hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 3, 1);
}
static void set_gxb_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
{
switch (clk) {
case 5940000:
@@ -191,7 +264,7 @@ static void set_gxb_hpll_clk_out(unsigned int clk)
}
}
static void set_gxtvbb_hpll_clk_out(unsigned int clk)
static void set_gxtvbb_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
{
switch (clk) {
case 5940000:
@@ -311,18 +384,23 @@ static void set_gxtvbb_hpll_clk_out(unsigned int clk)
static void set_hpll_clk_out(unsigned int clk)
{
pr_info("config HPLL = %d\n", clk);
uint32_t frac_rate;
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
set_gxb_hpll_clk_out(clk);
frac_rate = hdev->frac_rate_policy;
pr_info("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
switch (hdev->chip_type) {
case MESON_CPU_ID_GXBB:
set_gxb_hpll_clk_out(frac_rate, clk);
break;
case MESON_CPU_MAJOR_ID_GXTVBB:
set_gxtvbb_hpll_clk_out(clk);
case MESON_CPU_ID_GXTVBB:
set_gxtvbb_hpll_clk_out(frac_rate, clk);
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
case MESON_CPU_MAJOR_ID_TXLX:
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
case MESON_CPU_ID_TXLX:
set_gxl_hpll_clk_out(frac_rate, clk);
break;
default:
@@ -335,13 +413,15 @@ static void set_hpll_clk_out(unsigned int clk)
/* HERE MUST BE BIT OPERATION!!! */
static void set_hpll_sspll(enum hdmi_vic vic)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (hdev->chip_type) {
case MESON_CPU_ID_GXBB:
break;
case MESON_CPU_MAJOR_ID_GXTVBB:
case MESON_CPU_ID_GXTVBB:
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
set_hpll_sspll_gxl(vic);
break;
default:
@@ -351,9 +431,11 @@ static void set_hpll_sspll(enum hdmi_vic vic)
static void set_hpll_od1(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (hdev->chip_type) {
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 16, 2);
@@ -371,8 +453,8 @@ static void set_hpll_od1(unsigned int div)
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
set_hpll_od1_gxl(div);
break;
@@ -381,9 +463,11 @@ static void set_hpll_od1(unsigned int div)
static void set_hpll_od2(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (hdev->chip_type) {
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 22, 2);
@@ -401,8 +485,8 @@ static void set_hpll_od2(unsigned int div)
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
set_hpll_od2_gxl(div);
break;
@@ -411,9 +495,11 @@ static void set_hpll_od2(unsigned int div)
static void set_hpll_od3(unsigned int div)
{
switch (get_cpu_type()) {
case MESON_CPU_MAJOR_ID_GXBB:
case MESON_CPU_MAJOR_ID_GXTVBB:
struct hdmitx_dev *hdev = get_hdmitx_device();
switch (hdev->chip_type) {
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_GXTVBB:
switch (div) {
case 1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0, 18, 2);
@@ -431,8 +517,8 @@ static void set_hpll_od3(unsigned int div)
break;
}
break;
case MESON_CPU_MAJOR_ID_GXL:
case MESON_CPU_MAJOR_ID_GXM:
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
set_hpll_od3_gxl(div);
break;
@@ -744,13 +830,35 @@ static struct hw_enc_clk_val_group setting_3dfp_enc_clk_val[] = {
3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
};
static void hdmitx_set_clk_(enum hdmi_vic vic, enum hdmi_color_depth cd)
static void hdmitx_set_clk_(struct hdmitx_dev *hdev)
{
int i = 0;
int j = 0;
struct hw_enc_clk_val_group *p_enc = NULL;
enum hdmi_vic vic = hdev->cur_VIC;
enum hdmi_color_space cs = hdev->para->cs;
enum hdmi_color_depth cd = hdev->para->cd;
if (cd == COLORDEPTH_24B) {
/* YUV 422 always use 24B mode */
if (cs == COLORSPACE_YUV422)
cd = COLORDEPTH_24B;
if (hdev->flag_3dfp) {
p_enc = &setting_3dfp_enc_clk_val[0];
for (j = 0; j < sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
} else if (cd == COLORDEPTH_24B) {
p_enc = &setting_enc_clk_val_24[0];
for (j = 0; j < sizeof(setting_enc_clk_val_24)
/ sizeof(struct hw_enc_clk_val_group); j++) {
@@ -800,9 +908,11 @@ static void hdmitx_set_clk_(enum hdmi_vic vic, enum hdmi_color_depth cd)
return;
}
next:
set_hdmitx_sys_clk();
hdmitx_set_cts_sys_clk(hdev);
set_hpll_clk_out(p_enc[j].hpll_clk_out);
if ((cd == COLORDEPTH_24B) && sspll_en)
/* 4K mode doesn't enable SS*/
if ((cd == COLORDEPTH_24B) && (hdev->sspll)
&& (p_enc[j].hpll_clk_out != 5940000))
set_hpll_sspll(vic);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
@@ -815,41 +925,6 @@ next:
set_enci_div(p_enc[j].enci_div);
}
static void hdmitx_set_3dfp_clk(enum hdmi_vic vic)
{
int i = 0;
int j = 0;
struct hw_enc_clk_val_group *p_enc = NULL;
p_enc = &setting_3dfp_enc_clk_val[0];
for (j = 0; j < sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group); j++) {
for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
!= HDMI_VIC_END)); i++) {
if (vic == p_enc[j].group[i])
goto next;
}
}
if (j == sizeof(setting_3dfp_enc_clk_val)
/ sizeof(struct hw_enc_clk_val_group)) {
pr_info("Not find VIC = %d for hpll setting\n", vic);
return;
}
next:
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_sspll(vic);
set_hpll_od1(p_enc[j].od1);
set_hpll_od2(p_enc[j].od2);
set_hpll_od3(p_enc[j].od3);
set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
pr_info("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
set_vid_clk_div(p_enc[j].vid_clk_div);
set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
set_encp_div(p_enc[j].encp_div);
set_enci_div(p_enc[j].enci_div);
}
static int likely_frac_rate_mode(char *m)
{
if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
@@ -859,32 +934,26 @@ static int likely_frac_rate_mode(char *m)
return 0;
}
void hdmitx_set_clk(struct hdmitx_dev *hdev)
static void hdmitx_check_frac_rate(struct hdmitx_dev *hdev)
{
enum hdmi_vic vic = hdev->cur_VIC;
struct hdmi_format_para *para = NULL;
frac_rate = hdev->frac_rate_policy;
pr_info("hdmitx: set clk: VIC = %d cd = %d frac_rate = %d\n", vic,
hdev->para->cd, frac_rate);
para = hdmi_get_fmt_paras(vic);
if (para && (para->name) && likely_frac_rate_mode(para->name))
;
else {
pr_info("hdmitx: %s doesn't have frac_rate\n", para->name);
frac_rate = 0;
pr_info("%s doesn't have frac_rate\n", para->name);
hdev->frac_rate_policy = 0;
}
if (hdev->flag_3dfp) {
hdmitx_set_3dfp_clk(vic);
return;
}
if (hdev->para->cs != COLORSPACE_YUV422)
hdmitx_set_clk_(vic, hdev->para->cd);
else
hdmitx_set_clk_(vic, COLORDEPTH_24B);
pr_info("frac_rate = %d\n", hdev->frac_rate_policy);
}
MODULE_PARM_DESC(sspll_en, "\n hdmitx sspll_en\n");
module_param(sspll_en, int, 0664);
void hdmitx_set_clk(struct hdmitx_dev *hdev)
{
hdmitx_check_frac_rate(hdev);
hdmitx_set_clk_(hdev);
}

8
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.h
View File

@@ -53,6 +53,14 @@ struct hw_enc_clk_val_group {
};
void hdmitx_set_clk(struct hdmitx_dev *hdev);
void hdmitx_set_cts_sys_clk(struct hdmitx_dev *hdev);
void hdmitx_set_top_pclk(struct hdmitx_dev *hdev);
void hdmitx_set_hdcp_pclk(struct hdmitx_dev *hdev);
void hdmitx_set_cts_hdcp22_clk(struct hdmitx_dev *hdev);
void hdmitx_set_sys_clk(struct hdmitx_dev *hdev, unsigned char flag);
void hdmitx_set_vclk2_encp(struct hdmitx_dev *hdev);
void hdmitx_set_vclk2_enci(struct hdmitx_dev *hdev);
#endif

82
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c
View File

@@ -16,8 +16,28 @@
*/
#include <linux/printk.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "common.h"
#include "mach_reg.h"
#include "reg_ops.h"
#include "txlx_reg.h"
unsigned int hdmitx_get_format_txlx(void)
{
return hd_read_reg(P_ISA_DEBUG_REG0);
}
/*
* hdmitx apb reset
* P_RESET0_REGISTER bit19 : hdmitx capb
* P_RESET2_REGISTER bit15 : hdmi system reset
* P_RESET2_REGISTER bit2 : hdmi tx
*/
void hdmitx_sys_reset_txlx(void)
{
hd_set_reg_bits(P_RESET0_REGISTER, 1, 19, 1);
hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1);
hd_set_reg_bits(P_RESET2_REGISTER, 1, 2, 1);
}
/*
* NAME PAD PINMUX GPIO
@@ -30,30 +50,45 @@ int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd)
{
int ret = 0;
struct hdmitx_dev *hdev = get_hdmitx_device();
if (hdev->pdev == NULL) {
pr_info("exit for null device of hdmitx!\n");
return -ENODEV;
}
if (hdev->pdev->pins == NULL) {
pr_info("exit for null pins of hdmitx device!\n");
return -ENODEV;
}
if (hdev->pdev->pins->p == NULL) {
pr_info("exit for null pinctrl of hdmitx device pins!\n");
return -ENODEV;
}
switch (cmd) {
case HPD_INIT_DISABLE_PULLUP:
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 21, 1);
break;
case HPD_INIT_SET_FILTER:
hdmitx_wr_reg(HDMITX_TOP_HPD_FILTER,
((0xa << 12) | (0xa0 << 0)));
break;
case HPD_IS_HPD_MUXED:
ret = !!(hd_read_reg(P_PERIPHS_PIN_MUX_0) & (1 << 23));
ret = 1;
break;
case HPD_MUX_HPD:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 1, 23, 1);
pinctrl_select_state(hdev->pdev->pins->p,
hdev->pinctrl_default);
break;
case HPD_UNMUX_HPD:
hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 0, 23, 1);
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 1, 21, 1);
pinctrl_select_state(hdev->pdev->pins->p, hdev->pinctrl_i2c);
break;
case HPD_READ_HPD_GPIO:
ret = !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 21));
ret = hdmitx_rd_reg(HDMITX_DWC_PHY_STAT0) & (1 << 1);
break;
default:
pr_info("error hpd cmd %d\n", cmd);
pr_err("error hpd cmd %d\n", cmd);
break;
}
return ret;
@@ -61,28 +96,41 @@ int hdmitx_hpd_hw_op_txlx(enum hpd_op cmd)
int read_hpd_gpio_txlx(void)
{
return !!(hd_read_reg(P_PREG_PAD_GPIO1_I) & (1 << 21));
return hdmitx_rd_reg(HDMITX_DWC_PHY_STAT0) & (1 << 1);
}
int hdmitx_ddc_hw_op_txlx(enum ddc_op cmd)
{
int ret = 0;
struct hdmitx_dev *hdev = get_hdmitx_device();
if (hdev->pdev == NULL) {
pr_info("exit for null device of hdmitx!\n");
return -ENODEV;
}
if (hdev->pdev->pins == NULL) {
pr_info("exit for null pins of hdmitx device!\n");
return -ENODEV;
}
if (hdev->pdev->pins->p == NULL) {
pr_info("exit for null pinctrl of hdmitx device pins!\n");
return -ENODEV;
}
switch (cmd) {
case DDC_INIT_DISABLE_PULL_UP_DN:
hd_set_reg_bits(P_PAD_PULL_UP_EN_REG1, 0, 22, 2);
hd_set_reg_bits(P_PAD_PULL_UP_REG1, 0, 22, 2);
break;
case DDC_MUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 22, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 3, 21, 2);
pinctrl_select_state(hdev->pdev->pins->p,
hdev->pinctrl_default);
break;
case DDC_UNMUX_DDC:
hd_set_reg_bits(P_PREG_PAD_GPIO1_EN_N, 3, 22, 2);
hd_set_reg_bits(P_PERIPHS_PIN_MUX_0, 0, 21, 2);
pinctrl_select_state(hdev->pdev->pins->p, hdev->pinctrl_i2c);
break;
default:
pr_info("error ddc cmd %d\n", cmd);
pr_err("error ddc cmd %d\n", cmd);
}
return ret;
}

4
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
View File

@@ -17,7 +17,7 @@
#ifndef __MACH_REG_H__
#define __MACH_REG_H__
#include <linux/amlogic/iomap.h>
#include <linux/delay.h>
struct reg_s {
@@ -273,7 +273,7 @@ void init_reg_map(unsigned int type);
#define AIU_HDMI_CLK_DATA_CTRL 0x152a /* register.h:2466 */
#define P_AIU_HDMI_CLK_DATA_CTRL CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
#define ISA_DEBUG_REG0 0x2600
#define ISA_DEBUG_REG0 0x00
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)

140
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
View File

@@ -30,19 +30,10 @@
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/io.h>
#include "mach_reg.h"
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
#include "common.h"
#include "hdmi_tx_reg.h"
static int dbg_en;
/*
* RePacket HDMI related registers rd/wr
*/
struct reg_map {
unsigned int phy_addr;
unsigned int size;
void __iomem *p;
};
#include "reg_ops.h"
/* For gxb/gxl/gxm */
static struct reg_map reg_maps_def[] = {
@@ -87,7 +78,7 @@ static struct reg_map reg_maps_def[] = {
/* For txlx */
static struct reg_map reg_maps_txlx[] = {
[CBUS_REG_IDX] = { /* CBUS */
.phy_addr = 0xffd00000,
.phy_addr = 0xffd0f000,
.size = 0xa00000,
},
[PERIPHS_REG_IDX] = { /* PERIPHS */
@@ -131,23 +122,22 @@ void init_reg_map(unsigned int type)
int i;
switch (type) {
case 1:
case MESON_CPU_ID_TXLX:
map = reg_maps_txlx;
break;
default:
map = reg_maps_def;
break;
}
for (i = 0; i < REG_IDX_END; i++) {
map[i].p = ioremap(map[i].phy_addr, map[i].size);
if (!map[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
map[i].phy_addr);
} else {
pr_info("hdmitx20: Mapped PHY: 0x%x\n",
map[i].phy_addr);
for (i = 0; i < REG_IDX_END; i++) {
map[i].p = ioremap(map[i].phy_addr, map[i].size);
if (!map[i].p) {
pr_info("hdmitx20: failed Mapped PHY: 0x%x\n",
map[i].phy_addr);
} else {
pr_info("hdmitx20: Mapped PHY: 0x%x\n",
map[i].phy_addr);
}
}
break;
}
}
@@ -170,11 +160,46 @@ unsigned int hd_read_reg(unsigned int addr)
{
unsigned int val = 0;
unsigned int paddr = TO_PHY_ADDR(addr);
unsigned int index = (addr) >> BASE_REG_OFFSET;
val = readl(TO_PMAP_ADDR(addr));
struct hdmitx_dev *hdev = get_hdmitx_device();
if (dbg_en)
pr_info("Rd[0x%x] 0x%x\n", paddr, val);
switch (hdev->chip_type) {
case MESON_CPU_ID_TXLX:
switch (index) {
case CBUS_REG_IDX:
case RESET_CBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
val = aml_read_cbus(addr);
break;
case VCBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
val = aml_read_vcbus(addr);
break;
case AOBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
val = aml_read_aobus(addr);
break;
case HHI_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
val = aml_read_hiubus(addr);
break;
default:
break;
}
break;
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
val = readl(TO_PMAP_ADDR(addr));
break;
}
pr_debug(REG "Rd[0x%x] 0x%x\n", paddr, val);
return val;
}
@@ -182,11 +207,46 @@ unsigned int hd_read_reg(unsigned int addr)
void hd_write_reg(unsigned int addr, unsigned int val)
{
unsigned int paddr = TO_PHY_ADDR(addr);
unsigned int index = (addr) >> BASE_REG_OFFSET;
writel(val, TO_PMAP_ADDR(addr));
struct hdmitx_dev *hdev = get_hdmitx_device();
if (dbg_en)
pr_info("Wr[0x%x] 0x%x\n", paddr, val);
switch (hdev->chip_type) {
case MESON_CPU_ID_TXLX:
switch (index) {
case CBUS_REG_IDX:
case RESET_CBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
aml_write_cbus(addr, val);
break;
case VCBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
aml_write_vcbus(addr, val);
break;
case AOBUS_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
aml_write_aobus(addr, val);
break;
case HHI_REG_IDX:
addr &= ~(index << BASE_REG_OFFSET);
addr >>= 2;
aml_write_hiubus(addr, val);
break;
default:
break;
}
break;
case MESON_CPU_ID_GXL:
case MESON_CPU_ID_GXM:
default:
writel(val, TO_PMAP_ADDR(addr));
break;
}
pr_debug(REG "Wr[0x%x] 0x%x\n", paddr, val);
}
void hd_set_reg_bits(unsigned int addr, unsigned int value,
@@ -218,8 +278,7 @@ unsigned int hdmitx_rd_reg(unsigned int addr)
);
data = (unsigned int)(x0&0xffffffff);
if (dbg_en)
pr_info("%s rd[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
pr_debug(REG "%s rd[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
addr, data);
return data;
}
@@ -227,6 +286,7 @@ unsigned int hdmitx_rd_reg(unsigned int addr)
void hdmitx_wr_reg(unsigned int addr, unsigned int data)
{
unsigned long offset = (addr & DWC_OFFSET_MASK) >> 24;
register long x0 asm("x0") = 0x82000019;
register long x1 asm("x1") = (unsigned long)addr;
register long x2 asm("x2") = data;
@@ -239,8 +299,7 @@ void hdmitx_wr_reg(unsigned int addr, unsigned int data)
: : "r"(x0), "r"(x1), "r"(x2)
);
if (dbg_en)
pr_info("%s wr[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
pr_debug("%s wr[0x%x] 0x%x\n", offset ? "DWC" : "TOP",
addr, data);
}
@@ -265,7 +324,7 @@ void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout)
mdelay(2);
}
if (time_after(jiffies, time + timeout))
pr_info("hdmitx poll:0x%x val:0x%x T1=%lu t=%lu T2=%lu timeout\n",
pr_info(REG "hdmitx poll:0x%x val:0x%x T1=%lu t=%lu T2=%lu timeout\n",
addr, val, time, timeout, jiffies);
}
@@ -273,15 +332,12 @@ void hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
unsigned int mask)
{
unsigned long rd_data;
rd_data = hdmitx_rd_reg(addr);
if ((rd_data | mask) != (exp_data | mask)) {
pr_info("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
pr_info(REG "HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
(unsigned int)addr, (unsigned int)rd_data);
pr_info("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
pr_info(REG "Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
(unsigned int)exp_data, (unsigned int)mask);
}
}
MODULE_PARM_DESC(dbg_en, "\n debug_level\n");
module_param(dbg_en, int, 0664);

85
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __REG_OPS_H__
#define __REG_OPS_H__
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <linux/io.h>
#include <linux/amlogic/iomap.h>
/*
* RePacket HDMI related registers rd/wr
*/
struct reg_map {
unsigned int phy_addr;
unsigned int size;
void __iomem *p;
};
#define CBUS_REG_IDX 0
#define PERIPHS_REG_IDX 1
#define VCBUS_REG_IDX 2
#define AOBUS_REG_IDX 3
#define HHI_REG_IDX 4
#define RESET_CBUS_REG_IDX 5
#define HDMITX_REG_IDX 6
#define HDMITX_SEC_REG_IDX 7
#define ELP_ESM_REG_IDX 8
#define REG_IDX_END 9
#define BASE_REG_OFFSET 24
#define CBUS_REG_ADDR(reg) \
((CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define PERIPHS_REG_ADDR(reg) \
((PERIPHS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define VCBUS_REG_ADDR(reg) \
((VCBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define AOBUS_REG_ADDR(reg) \
((AOBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define HHI_REG_ADDR(reg) \
((HHI_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define RESET_CBUS_REG_ADDR(reg) \
((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define HDMITX_SEC_REG_ADDR(reg) \
((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define HDMITX_REG_ADDR(reg) \
((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
#define ELP_ESM_REG_ADDR(reg) \
((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
extern unsigned int hd_read_reg(unsigned int addr);
extern void hd_write_reg(unsigned int addr, unsigned int val);
extern void hd_set_reg_bits(unsigned int addr, unsigned int value,
unsigned int offset, unsigned int len);
extern void init_reg_map(unsigned int type);
#endif

6
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/tvenc_conf.h
View File

@@ -15,7 +15,7 @@
*
*/
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h>
#include <linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h>
void set_vmode_enc_hw(enum hdmi_vic vic);
void set_vmode_3dfp_enc_hw(enum hdmi_vic vic); /* For 3D Frame Packing */
void set_vmode_enc_hw(struct hdmitx_dev *hdev);

30
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __TXLX_REG_H__
#define __TXLX_REG_H__
#include "reg_ops.h"
#define RESET0_REGISTER 0x1001
#define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER)
#define RESET2_REGISTER 0x1003
#define P_RESET2_REGISTER RESET_CBUS_REG_ADDR(RESET2_REGISTER)
#define ISA_DEBUG_REG0 0x3c00
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
#endif

12
include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h
View File

@@ -20,8 +20,6 @@
#include "hdmi_common.h"
/* old definitions move to hdmi_common.h */
enum hdmi_rx_video_state {
STATE_VIDEO__POWERDOWN = 0,
STATE_VIDEO__MUTED = 1,
@@ -271,16 +269,6 @@ struct vsdb_phyaddr {
unsigned char valid;
};
struct hdmitx_clk {
enum hdmi_vic vic;
uint64_t clk_sys;
uint64_t clk_phy;
uint64_t clk_vid;
uint64_t clk_encp;
uint64_t clk_enci;
uint64_t clk_pixel;
};
#define Y420CMDB_MAX 32
struct hdmitx_info {
struct hdmi_rx_audioinfo audio_info;

134
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -24,7 +24,22 @@
#include <linux/cdev.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
/* #include <linux/amlogic/aml_gpio_consumer.h> */
#include <linux/pinctrl/consumer.h>
/* HDMITX driver version */
#define HDMITX_VER "20171127"
/* chip type */
#define MESON_CPU_ID_M8B 0
#define MESON_CPU_ID_GXBB 1
#define MESON_CPU_ID_GXTVBB 2
#define MESON_CPU_ID_GXL 3
#define MESON_CPU_ID_GXM 4
#define MESON_CPU_ID_TXL 5
#define MESON_CPU_ID_TXLX 6
#define MESON_CPU_ID_AXG 7
#define MESON_CPU_ID_GXLX 8
#define MESON_CPU_ID_TXHD 9
/*****************************
* hdmitx attr management
@@ -194,10 +209,17 @@ enum hdmi_hdr_color {
C_BT2020,
};
struct hdmitx_clk_tree_s {
/* hdmitx clk tree */
struct clk *hdcp22_tx_skp;
struct clk *hdcp22_tx_esm;
};
#define EDID_MAX_BLOCK 4
#define HDMI_TMP_BUF_SIZE 1024
struct hdmitx_dev {
struct cdev cdev; /* The cdev structure */
dev_t hdmitx_id;
struct proc_dir_entry *proc_file;
struct task_struct *task;
struct task_struct *task_monitor;
@@ -206,6 +228,9 @@ struct hdmitx_dev {
struct workqueue_struct *hdmi_wq;
struct workqueue_struct *rxsense_wq;
struct device *hdtx_dev;
struct device *pdev; /* for pinctrl*/
struct pinctrl_state *pinctrl_i2c;
struct pinctrl_state *pinctrl_default;
struct delayed_work work_hpd_plugin;
struct delayed_work work_hpd_plugout;
struct delayed_work work_rxsense;
@@ -216,15 +241,19 @@ struct hdmitx_dev {
struct delayed_work cec_work;
#endif
struct timer_list hdcp_timer;
const char *hpd_pin;
const char *ddc_pin;
int chip_type;
int hdcp_try_times;
int chip_type;
int hdmi_init;
int hpdmode;
/* -1, no hdcp; 0, NULL; 1, 1.4; 2, 2.2 */
int hdcp_mode;
int hdcp_bcaps_repeater;
int ready; /* 1, hdmi stable output, others are 0 */
int hdcp_hpd_stick; /* 1 not init & reset at plugout */
int hdcp_tst_sig;
bool hdcp22_type;
unsigned int div40;
unsigned int lstore;
struct {
void (*SetPacket)(int type, unsigned char *DB,
unsigned char *HB);
@@ -263,28 +292,28 @@ struct hdmitx_dev {
struct hdmi_config_platform_data config_data;
enum hdmi_event_t hdmitx_event;
unsigned int irq_hpd;
/* wait_queue_head_t wait_queue;*/
/*EDID*/
unsigned int cur_edid_block;
unsigned int cur_phy_block_ptr;
unsigned char EDID_buf[EDID_MAX_BLOCK * 128];
unsigned char EDID_buf1[EDID_MAX_BLOCK*128]; /* for second read */
unsigned char tmp_edid_buf[128*EDID_MAX_BLOCK];
unsigned char *edid_ptr;
unsigned int edid_parsing; /* Indicator that RX edid data integrated */
unsigned char EDID_hash[20];
struct rx_cap RXCap;
struct hdmitx_vidpara *cur_video_param;
int vic_count;
struct hdmitx_clk_tree_s hdmitx_clk_tree;
/*audio*/
struct hdmitx_audpara cur_audio_param;
int audio_param_update_flag;
/*status*/
#define DISP_SWITCH_FORCE 0
#define DISP_SWITCH_EDID 1
unsigned char disp_switch_config; /* 0, force; 1,edid */
unsigned char unplug_powerdown;
unsigned short physical_addr;
unsigned int cur_VIC;
char fmt_attr[16];
atomic_t kref_video_mute;
atomic_t kref_audio_mute;
/**/
unsigned char hpd_event; /* 1, plugin; 2, plugout */
unsigned char hpd_state; /* 1, connect; 0, disconnect */
@@ -309,9 +338,17 @@ struct hdmitx_dev {
/* 0.1% clock shift, 1080p60hz->59.94hz */
unsigned int frac_rate_policy;
unsigned int rxsense_policy;
unsigned int sspll;
/* configure for I2S: 8ch in, 2ch out */
/* 0: default setting 1:ch0/1 2:ch2/3 3:ch4/5 4:ch6/7 */
unsigned int aud_output_ch;
unsigned int hdmi_ch;
unsigned int tx_aud_src; /* 0: SPDIF 1: I2S */
/* if set to 1, then HDMI will output no audio */
/* In KTV case, HDMI output Picture only, and Audio is driven by other
* sources.
*/
unsigned char hdmi_audio_off_flag;
enum hdmi_hdr_transfer hdr_transfer_feature;
enum hdmi_hdr_color hdr_color_feature;
unsigned int sdr_hdr_feature;
@@ -337,7 +374,6 @@ struct hdmitx_dev {
#define HDCP14_OFF 0x2
#define HDCP22_ON 0x3
#define HDCP22_OFF 0x4
#define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04)
#define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05)
#define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06)
#define DDC_HDCP_GET_AUTH (CMD_DDC_OFFSET + 0x07)
@@ -345,7 +381,6 @@ struct hdmitx_dev {
#define PIN_MUX 0x1
#define PIN_UNMUX 0x2
#define DDC_EDID_READ_DATA (CMD_DDC_OFFSET + 0x0a)
#define DDC_IS_EDID_DATA_READY (CMD_DDC_OFFSET + 0x0b)
#define DDC_EDID_GET_DATA (CMD_DDC_OFFSET + 0x0c)
#define DDC_EDID_CLEAR_RAM (CMD_DDC_OFFSET + 0x0d)
#define DDC_HDCP_MUX_INIT (CMD_DDC_OFFSET + 0x0e)
@@ -358,23 +393,9 @@ struct hdmitx_dev {
* CONFIG CONTROL //CntlConfig
**********************************************************************/
/* Video part */
#define CONF_VIDEO_BLANK_OP (CMD_CONF_OFFSET + 0x00)
#define VIDEO_BLANK 0x1
#define VIDEO_UNBLANK 0x2
#define CONF_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x02)
#define HDMI_MODE 0x1
#define DVI_MODE 0x2
#define CONF_SYSTEM_ST (CMD_CONF_OFFSET + 0x03)
/* Audio part */
#define CONF_CLR_AVI_PACKET (CMD_CONF_OFFSET + 0x04)
#define CONF_CLR_VSDB_PACKET (CMD_CONF_OFFSET + 0x05)
#define CONF_VIDEO_MAPPING (CMD_CONF_OFFSET + 0x06)
#define CONF_GET_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x07)
#define CONF_AUDIO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x00)
#define AUDIO_MUTE 0x1
#define AUDIO_UNMUTE 0x2
#define CONF_CLR_AUDINFO_PACKET (CMD_CONF_OFFSET + 0x1000 + 0x01)
#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
#define CLR_AVI_BT2020 0x0
#define SET_AVI_BT2020 0x1
@@ -393,6 +414,17 @@ struct hdmitx_dev {
#define VIDEO_MUTE 0x1
#define VIDEO_UNMUTE 0x2
/* Audio part */
#define CONF_CLR_AVI_PACKET (CMD_CONF_OFFSET + 0x04)
#define CONF_CLR_VSDB_PACKET (CMD_CONF_OFFSET + 0x05)
#define CONF_VIDEO_MAPPING (CMD_CONF_OFFSET + 0x06)
#define CONF_GET_HDMI_DVI_MODE (CMD_CONF_OFFSET + 0x07)
#define CONF_AUDIO_MUTE_OP (CMD_CONF_OFFSET + 0x1000 + 0x00)
#define AUDIO_MUTE 0x1
#define AUDIO_UNMUTE 0x2
#define CONF_CLR_AUDINFO_PACKET (CMD_CONF_OFFSET + 0x1000 + 0x01)
/***********************************************************************
* MISC control, hpd, hpll //CntlMisc
**********************************************************************/
@@ -451,12 +483,9 @@ struct hdmitx_dev {
/* reduce a little time, previous setting is 4000/10 */
#define AUTH_PROCESS_TIME (1000/100)
#define HDMITX_VER "20170622"
/***********************************************************************
* hdmitx protocol level interface
**********************************************************************/
extern void hdmitx_init_parameters(struct hdmitx_info *info);
extern enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode);
extern int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device);
@@ -532,7 +561,7 @@ extern int hdmi_set_3d(struct hdmitx_dev *hdmitx_device, int type,
unsigned int param);
extern int hdmitx_set_audio(struct hdmitx_dev *hdmitx_device,
struct hdmitx_audpara *audio_param, int hdmi_ch);
struct hdmitx_audpara *audio_param);
/* for notify to cec */
#define HDMITX_PLUG 1
@@ -553,7 +582,7 @@ static inline struct hdmitx_dev *get_hdmitx_device(void)
}
static inline int get_hpd_state(void)
{
return -1;
return 0;
}
static inline int hdmitx_event_notifier_regist(struct notifier_block *nb)
{
@@ -566,28 +595,17 @@ static inline int hdmitx_event_notifier_unregist(struct notifier_block *nb)
}
#endif
extern int hdmi_print_buf(char *buf, int len);
extern void hdmi_set_audio_para(int para);
extern void hdmitx_output_rgb(void);
extern int get_cur_vout_index(void);
extern struct vinfo_s *hdmi_get_current_vinfo(void);
void phy_pll_off(void);
extern void phy_pll_off(void);
extern int get_hpd_state(void);
void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev);
extern void hdmitx_hdcp_do_work(struct hdmitx_dev *hdev);
/***********************************************************************
* hdmitx hardware level interface
***********************************************************************/
/* #define DOUBLE_CLK_720P_1080I */
extern unsigned char hdmi_pll_mode; /* 1, use external clk as hdmi pll source */
extern void HDMITX_Meson_Init(struct hdmitx_dev *hdmitx_device);
extern unsigned char hdmi_audio_off_flag;
extern unsigned int get_hdcp22_base(void);
/*
* hdmitx_audio_mute_op() is used by external driver call
@@ -637,34 +655,4 @@ struct Hdcp_Sub {
unsigned int hdcp_sub_len;
};
/***********************************************************************
* hdmi debug printk
* level: 0 ~ 4 Default is 2
* 0: ERRor 1: IMPortant 2: INFormative 3: DETtal 4: LOW
* hdmi_print(ERR, EDID "edid bad\");
* hdmi_print(IMP, AUD "set audio format: AC-3\n");
* hdmi_print(DET)
**********************************************************************/
#define HD "hdmitx: "
#define VID HD "video: "
#define AUD HD "audio: "
#define CEC HD "cec: "
#define EDID HD "edid: "
#define HDCP HD "hdcp: "
#define SYS HD "system: "
#define HPD HD "hpd: "
#define ERR 1
#define IMP 2
#define INF 3
#define LOW 4
#define DET (5, "%s[%d]", __func__, __LINE__)
extern void hdmi_print(int level, const char *fmt, ...);
#define dd()
#ifndef dd
#error delete debug information
#endif
#endif