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phy: rockchip: usbdp: init flip variable in fixed lane mux case

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It should be initialized the USB flip for fixed lane mapping case
if the USB lanes are assigned. The ln0/ln1 is normal (!flip) and ln2/ln3
is reverse (flip).

This also amend "rx cdr lock timeout" log level to notice since it
may not cause the functional defect in most cases.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I693f772b87df97581a60f89219ec4dc6cafb79a3
This commit is contained in:
Frank Wang
2022-11-30 09:49:38 +08:00
committed by Tao Huang
parent cd10522093
commit f07500720b
1 changed files with 13 additions and 10 deletions
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23
drivers/phy/rockchip/phy-rockchip-usbdp.c
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@@ -668,14 +668,15 @@ static int udphy_disable(struct rockchip_udphy *udphy)
return 0;
}
static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np)
static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device *dev)
{
struct device_node *np = dev->of_node;
struct property *prop;
int ret, i, len, num_lanes;
prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
if (!prop) {
dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
udphy->mode = UDPHY_MODE_USB;
return 0;
}
@@ -683,13 +684,13 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
num_lanes = len / sizeof(u32);
if (num_lanes != 2 && num_lanes != 4) {
dev_err(udphy->dev, "invalid number of lane mux\n");
dev_err(dev, "invalid number of lane mux\n");
return -EINVAL;
}
ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
if (ret) {
dev_err(udphy->dev, "get dp lane mux failed\n");
dev_err(dev, "get dp lane mux failed\n");
return -EINVAL;
}
@@ -697,7 +698,7 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
int j;
if (udphy->dp_lane_sel[i] > 3) {
dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
return -EINVAL;
}
@@ -705,15 +706,17 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
for (j = i + 1; j < num_lanes; j++) {
if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
dev_err(udphy->dev, "set repeat lane mux value\n");
dev_err(dev, "set repeat lane mux value\n");
return -EINVAL;
}
}
}
udphy->mode = UDPHY_MODE_DP;
if (num_lanes == 2)
if (num_lanes == 2) {
udphy->mode |= UDPHY_MODE_USB;
udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
}
return 0;
}
@@ -788,7 +791,7 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
}
}
ret = udphy_parse_lane_mux_data(udphy, np);
ret = udphy_parse_lane_mux_data(udphy, dev);
if (ret)
return ret;
@@ -1341,14 +1344,14 @@ static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
200, 100000);
if (ret)
dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
} else {
ret = regmap_read_poll_timeout(udphy->pma_regmap,
TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
200, 100000);
if (ret)
dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
}
}