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clk: rockchip: fix up frac clk parent no update

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For some special conditions, the parent clock of fractional
is not updated correctly.
before clk summary:
clk_spdif2_dp0_src
	clk_spdif2_dp0
		mclk_spdif2
		mclk_spdif2_dp0
	clk_spdif2_dp0_frac
after clk summary:
clk_spdif2_dp0_src
	clk_spdif2_dp0_frac
		clk_spdif2_dp0
			mclk_spdif2
			mclk_spdif2_dp0

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I9e9027774bf25f0f0ea6d8df6491a7feef4ffc48
This commit is contained in:
Elaine Zhang
2022-11-24 16:24:45 +08:00
committed by Tao Huang
parent 37158d1f2b
commit cd10522093
1 changed files with 3 additions and 0 deletions
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3
drivers/clk/rockchip/clk.c
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@@ -154,6 +154,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
frac->mux_ops->set_parent(&frac_mux->hw,
frac->mux_frac_idx);
frac->rate_change_remuxed = 1;
clk_hw_set_parent(&frac_mux->hw,
clk_hw_get_parent_by_index(&frac_mux->hw,
frac->mux_frac_idx));
}
} else if (event == POST_RATE_CHANGE) {
/*