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drm/rockchip: vop2: support use video port default parent

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When video port output image under 4K@60Hz(dclk less than 600MHz),
The dclk parent use hdmi0 phy pll or hdmi1 phy pll. In some cases
the hdmi0 phy pll or hdmi1 phy pll is not enough for all output
interface. For example, hdmi0 and hdmi0 connect to video port0 and
dp connect to video port1. In this case, It need the video port1
need use default dclk parent.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icdf050bb1e7a9f36022f5dd196358136c1d9242c
This commit is contained in:
Zhang Yubing
2022-03-08 10:39:22 +08:00
committed by Tao Huang
parent 817db0024a
commit f283539a10
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -3664,8 +3664,8 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
hdmi1_phy_pll->vp_mask |= BIT(vp->id);
} else {
DRM_ERROR("No free hdmi phy pll for DP\n");
return -EBUSY;
vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
DRM_INFO("No free hdmi phy pll for DP, use default parent\n");
}
}
} else {