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clk: rockchip: rk3568: support hdmi setting clk

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Note:
Dclk_vop0, exclusive HPLL, DCLK_VOP0 and HPLL is 1:1 relationship.
dts need setting parent as:
assigned-clocks = <&cru DCLK_VOP0>;
assigned-clock-parents = <&pmucru PLL_HPLL>;

Dclk_vop1, exclusive VPLL, DCLK_VOP1 and VPLL is 1:n relationship.
n = DIV_ROUND_UP(600M, DCLk_rate)
dts need setting parent as:
assigned-clocks = <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_VPLL>;

Dclk_vop2, no exclusive PLL, GPLL\CPLL\VPLL or HPLL near
frequency division.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I3172025737e544c8989ab9fabe0e7ba06d6db1db
This commit is contained in:
Elaine Zhang
2020-11-10 09:43:16 +08:00
committed by Tao Huang
parent de16379976
commit f55add63e6
1 changed files with 5 additions and 3 deletions
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8
drivers/clk/rockchip/clk-rk3568.c
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@@ -79,8 +79,10 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
{ /* sentinel */ },
};
@@ -1078,12 +1080,12 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(20), 8, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
RK3568_CLKGATE_CON(20), 9, GFLAGS),
COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 0,
COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 10, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 0,
COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 11, GFLAGS),
RK3568_CLKGATE_CON(20), 11, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE),
COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 12, GFLAGS),