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mmc: dw_mmc-rockchip: Fix internal phase calculate

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ciu clock from CRU is 2 times of interface clock, so the delay number
maybe not so accurate as the sample phase is based on interface clock.

Change-Id: Ib8d66f1c7af18fa3888dafc4528a95aabfa8572f
Fixes: 1505eda5b9 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2024-06-12 16:06:06 +08:00
parent 43675f80cc
commit f5f09fbd44
1 changed files with 2 additions and 2 deletions
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4
drivers/mmc/host/dw_mmc-rockchip.c
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@@ -48,7 +48,7 @@ struct dw_mci_rockchip_priv_data {
*/
static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
{
unsigned long rate = clk_get_rate(host->ciu_clk);
unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
u32 raw_value;
u16 degrees;
u32 delay_num = 0;
@@ -79,7 +79,7 @@ static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees)
{
unsigned long rate = clk_get_rate(host->ciu_clk);
unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
u8 nineties, remainder;
u8 delay_num;
u32 raw_value;