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* commit 'c1ccd0e0654dac345c1c50b703df63ff1f4c8f4b': (40 commits)
  media: i2c: imx415: adjusting the power on timing
  arm64: configs: add rk3588_vehicle.config
  media: i2c: rk628: set default timings when query timing if hdmi unplug
  drm/rockchip: dw-dp: support more color format
  media: i2c: rk628: add CSI error interrupts to haldle csi errors
  media: i2c: rk628: fix get capture when capture mode is 0
  arm64: dts: rockchip: px30-evb-ddr3-v10: reduce power consumption by reducing voltage
  media: i2c: maxim: driver version v3.01.00
  arm64: dts: rockchip: rk3588-evb7-imx415: remove cam_ircut0
  media: i2c: sc450ai adapt sleep_wakeup
  media: i2c: rk628: fix CTS HF2-23 test fail
  media: i2c: rk628: fix CTS HF2-86 test fail
  media: i2c: rk628: fix CTS test fail
  media: i2c: rk628: add hdmirx cec support
  media: i2c: rk628: disable character error detection
  media: i2c: rk628: fix resolution change but not recognized
  ARM: dts: rockchip: rv1106g-evb2-v12-wakeup: fix false wakeup issue
  drm/rockchip: vop: add csc_mode regs for PX30/RK3366/RV1126
  arm64: dts: rockchip: rk3588-vehicle-evb-v22.dts: fix max96712 dphy3 lock gpio error
  input: sensor: fix compile errors on kernel-6.1
  ...

Change-Id: If6549823cc24e59e9bc0c049cc6784b0b24dfaf2

Conflicts:
	drivers/gpu/drm/rockchip/Kconfig
	drivers/gpu/drm/rockchip/Makefile
This commit is contained in:
Tao Huang
2024-01-24 11:23:31 +08:00
parent 7392e86034 c1ccd0e065
commit f65077b203
147 changed files with 1762 additions and 13863 deletions
Download Patch File Download Diff File Expand all files Collapse all files

121
arch/arm/boot/dts/rk3288-evb-rk628-hdmi2csi-avb.dts
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@@ -1,121 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
/dts-v1/;
#include "rk3288-evb-rk628.dtsi"
/ {
model = "Rockchip RK3288 EVB RK628 Board";
compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288";
chosen {
bootargs = "rootwait earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0 androidboot.selinux=permissive";
};
hdmiin-sound {
compatible = "rockchip,rockchip-rt5651-rk628-sound";
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5651>;
status = "okay";
};
};
&video_phy {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in_vopb {
status = "disabled";
};
&hdmi_in_vopl {
status = "okay";
};
&route_hdmi {
connect = <&vopl_out_hdmi>;
status = "disabled";
};
&rk628 {
reg = <0x51>;
interrupt-parent = <&gpio7>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&rk628_combrxphy {
status = "okay";
};
&rk628_combtxphy {
status = "okay";
};
&rk628_csi {
status = "okay";
plugin-det-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "RK628-CSI";
rockchip,camera-module-lens-name = "NC";
port {
hdmiin_out0: endpoint {
remote-endpoint = <&hdmi2mipi_in>;
data-lanes = <1 2 3 4>;
};
};
};
&mipi_phy_rx0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi2mipi_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmiin_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy_rx_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp_mipi_in>;
};
};
};
};
&rkisp1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_mipi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy_rx_out>;
};
};
};

333
arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts
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@@ -1,333 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
/dts-v1/;
#include "rk3288-evb-rk628.dtsi"
&rk628_dsi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in_post_process: endpoint {
remote-endpoint = <&post_process_out_dsi0>;
};
};
};
panel@0 {
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
init-delay-ms = <120>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM |
MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 ff 98 81 03
39 00 02 01 00
39 00 02 02 00
39 00 02 03 53
39 00 02 04 53
39 00 02 05 13
39 00 02 06 04
39 00 02 07 02
39 00 02 08 02
39 00 02 09 00
39 00 02 0a 00
39 00 02 0b 00
39 00 02 0c 00
39 00 02 0d 00
39 00 02 0e 00
39 00 02 0f 00
39 00 02 10 00
39 00 02 11 00
39 00 02 12 00
39 00 02 13 00
39 00 02 14 00
39 00 02 15 08
39 00 02 16 10
39 00 02 17 00
39 00 02 18 08
39 00 02 19 00
39 00 02 1a 00
39 00 02 1b 00
39 00 02 1c 00
39 00 02 1d 00
39 00 02 1e c0
39 00 02 1f 80
39 00 02 20 02
39 00 02 21 09
39 00 02 22 00
39 00 02 23 00
39 00 02 24 00
39 00 02 25 00
39 00 02 26 00
39 00 02 27 00
39 00 02 28 55
39 00 02 29 03
39 00 02 2a 00
39 00 02 2b 00
39 00 02 2c 00
39 00 02 2d 00
39 00 02 2e 00
39 00 02 2f 00
39 00 02 30 00
39 00 02 31 00
39 00 02 32 00
39 00 02 33 00
39 00 02 34 04
39 00 02 35 05
39 00 02 36 05
39 00 02 37 00
39 00 02 38 3c
39 00 02 39 35
39 00 02 3a 00
39 00 02 3b 40
39 00 02 3c 00
39 00 02 3d 00
39 00 02 3e 00
39 00 02 3f 00
39 00 02 40 00
39 00 02 41 88
39 00 02 42 00
39 00 02 43 00
39 00 02 44 1f
39 00 02 50 01
39 00 02 51 23
39 00 02 52 45
39 00 02 53 67
39 00 02 54 89
39 00 02 55 ab
39 00 02 56 01
39 00 02 57 23
39 00 02 58 45
39 00 02 59 67
39 00 02 5a 89
39 00 02 5b ab
39 00 02 5c cd
39 00 02 5d ef
39 00 02 5e 03
39 00 02 5f 14
39 00 02 60 15
39 00 02 61 0c
39 00 02 62 0d
39 00 02 63 0e
39 00 02 64 0f
39 00 02 65 10
39 00 02 66 11
39 00 02 67 08
39 00 02 68 02
39 00 02 69 0a
39 00 02 6a 02
39 00 02 6b 02
39 00 02 6c 02
39 00 02 6d 02
39 00 02 6e 02
39 00 02 6f 02
39 00 02 70 02
39 00 02 71 02
39 00 02 72 06
39 00 02 73 02
39 00 02 74 02
39 00 02 75 14
39 00 02 76 15
39 00 02 77 0f
39 00 02 78 0e
39 00 02 79 0d
39 00 02 7a 0c
39 00 02 7b 11
39 00 02 7c 10
39 00 02 7d 06
39 00 02 7e 02
39 00 02 7f 0a
39 00 02 80 02
39 00 02 81 02
39 00 02 82 02
39 00 02 83 02
39 00 02 84 02
39 00 02 85 02
39 00 02 86 02
39 00 02 87 02
39 00 02 88 08
39 00 02 89 02
39 00 02 8a 02
39 00 04 ff 98 81 04
39 00 02 00 80
39 00 02 70 00
39 00 02 71 00
39 00 02 66 fe
39 00 02 82 15
39 00 02 84 15
39 00 02 85 15
39 00 02 3a 24
39 00 02 32 ac
39 00 02 8c 80
39 00 02 3c f5
39 00 02 88 33
39 00 04 ff 98 81 01
39 00 02 22 0a
39 00 02 31 00
39 00 02 53 78
39 00 02 55 7b
39 00 02 60 20
39 00 02 61 00
39 00 02 62 0d
39 00 02 63 00
39 00 02 a0 00
39 00 02 a1 10
39 00 02 a2 1c
39 00 02 a3 13
39 00 02 a4 15
39 00 02 a5 26
39 00 02 a6 1a
39 00 02 a7 1d
39 00 02 a8 67
39 00 02 a9 1c
39 00 02 aa 29
39 00 02 ab 58
39 00 02 ac 26
39 00 02 ad 28
39 00 02 ae 5c
39 00 02 af 30
39 00 02 b0 31
39 00 02 b1 32
39 00 02 b2 00
39 00 02 c0 00
39 00 02 c1 10
39 00 02 c2 1c
39 00 02 c3 13
39 00 02 c4 15
39 00 02 c5 26
39 00 02 c6 1a
39 00 02 c7 1d
39 00 02 c8 67
39 00 02 c9 1c
39 00 02 ca 29
39 00 02 cb 5b
39 00 02 cc 26
39 00 02 cd 28
39 00 02 ce 5c
39 00 02 cf 30
39 00 02 d0 31
39 00 02 d1 2e
39 00 02 d2 32
39 00 02 d3 00
39 00 04 ff 98 81 00
05 fa 01 11
05 14 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <64000000>;
hactive = <720>;
vactive = <1280>;
hfront-porch = <40>;
hsync-len = <10>;
hback-porch = <40>;
vfront-porch = <22>;
vsync-len = <4>;
vback-porch = <11>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
&rk628_combtxphy {
status = "okay";
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&video_phy {
status = "okay";
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&vopb {
assigned-clocks = <&cru DCLK_VOP0>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
&vopl {
assigned-clocks = <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

95
arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
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@@ -1,95 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
/dts-v1/;
#include "rk3288-evb-rk628.dtsi"
&sound {
status = "okay";
};
&rk628_hdmi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_hdmi>;
};
};
};
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&video_phy {
status = "okay";
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&vopb {
assigned-clocks = <&cru DCLK_VOP0>;
assigned-clock-parents = <&cru PLL_CPLL>;
};
&vopl {
assigned-clocks = <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_GPLL>;
};

144
arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts
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@@ -1,144 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
/dts-v1/;
#include "rk3288-evb-rk628.dtsi"
/ {
model = "Rockchip RK3288 EVB RK628 Board";
compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288";
panel {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <48000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <90>;
hfront-porch = <90>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <90>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&rk628_lvds {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_post_process: endpoint {
remote-endpoint = <&post_process_out_lvds>;
};
};
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&rk628_combtxphy {
status = "okay";
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_lvds: endpoint {
remote-endpoint = <&lvds_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&video_phy {
status = "okay";
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&vopb {
assigned-clocks = <&cru DCLK_VOP0>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
&vopl {
assigned-clocks = <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

151
arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-dual-avb.dts
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@@ -1,151 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
/dts-v1/;
#include "rk3288-evb-rk628.dtsi"
/ {
vcc33_lcd: vcc33-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc33_lcd";
regulator-boot-on;
gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
panel {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc33_lcd>;
enable-gpios = <&gpio5 RK_PC1 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <149000000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <96>;
hfront-porch = <120>;
vback-porch = <8>;
vfront-porch = <33>;
hsync-len = <64>;
vsync-len = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&rk628_lvds {
rockchip,link-type = "dual-link-even-odd-pixels";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_post_process: endpoint {
remote-endpoint = <&post_process_out_lvds>;
};
};
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&rk628_combtxphy {
status = "okay";
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_lvds: endpoint {
remote-endpoint = <&lvds_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&video_phy {
status = "okay";
};
&rgb_in_vopb {
status = "disabled";
};
&rgb_in_vopl {
status = "okay";
};
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";
};
&vopb {
assigned-clocks = <&cru DCLK_VOP0>;
assigned-clock-parents = <&cru PLL_GPLL>;
};
&vopl {
assigned-clocks = <&cru DCLK_VOP1>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

614
arch/arm/boot/dts/rk3288-evb-rk628.dtsi
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@@ -1,614 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/input/input.h>
#include "rk3288.dtsi"
#include "rk3288-android.dtsi"
/ {
model = "Rockchip RK3288 EVB RK628 Board";
compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288";
chosen: chosen {
bootargs = "rootwait earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
vol-up-key {
label = "volume up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <1000>;
};
vol-down-key {
label = "volume down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <170000>;
};
menu {
label = "menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <640000>;
};
esc {
label = "esc";
linux,code = <KEY_ESC>;
press-threshold-microvolt = <1000000>;
};
home {
label = "home";
linux,code = <KEY_HOME>;
press-threshold-microvolt = <1300000>;
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 1000000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
};
i2s_mclkin: i2s-mclkin {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&cru SCLK_I2S0_OUT>;
clock-mult = <1>;
clock-div = <1>;
clock-output-names = "i2s_mclkin";
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "realtek,rt5651-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC1", "Microphone Jack",
"MIC2", "Microphone Jack",
"Microphone Jack", "micbias1",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
status = "disabled";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&rt5651>;
};
};
simple-audio-card,dai-link@1 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&rk628_hdmi>;
};
};
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-logic {
compatible = "pwm-regulator";
rockchip,pwm_id = <1>;
rockchip,pwm_voltage = <1100000>;
pwms = <&pwm1 0 25000 1>;
regulator-name = "vcc_log";
regulator-min-microvolt = <860000>;
regulator-max-microvolt = <1360000>;
regulator-always-on;
regulator-boot-on;
};
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
};
&backlight {
/delete-property/ enable-gpios;
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&dfi {
status = "okay";
};
&dmc {
center-supply = <&vdd_log>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_io>;
vcc12-supply = <&vcc_io>;
vddio-supply = <&vcc_io>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_tp: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_codec: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_codec";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vccio_wl: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vccio_wl";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_lcd: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sd: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio7>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio7 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
&i2c2 {
status = "okay";
rt5651: rt5651@1a {
compatible = "rockchip,rt5651";
reg = <0x1a>;
clocks = <&cru SCLK_I2S0_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
};
};
&i2s {
#sound-dai-cells = <0>;
status = "okay";
};
#include "rk628.dtsi"
&io_domains {
audio-supply = <&vcc_io>;
bb-supply = <&vcc_io>;
dvp-supply = <&vcc_io>;
flash0-supply = <&vcc_18>;
gpio30-supply = <&vcc_io>;
gpio1830 = <&vcc_io>;
lcdc-supply = <&vcc_lcd>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vccio_wl>;
status = "okay";
};
&rockchip_suspend {
rockchip,pwm-regulator-config = <
(0
| PWM1_REGULATOR_EN
)
>;
status = "okay";
};
&pwm0 {
status = "okay";
};
&pwm1 {
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin_pull_down>;
status = "okay";
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
max-frequency = <100000000>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
status = "okay";
};
&saradc {
vref-supply = <&vcc_18>;
status = "okay";
};
&sdmmc {
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
no-sdio;
no-mmc;
status = "okay";
};
&wdt {
status = "okay";
};
&pwm0 {
status = "okay";
};
&backlight {
status = "okay";
};
&rga {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&usbphy {
status = "okay";
};
&usb_host0_ehci {
rockchip-relinquish-port;
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1 {
status = "okay";
};
&usb_otg {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
};
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
/*
* Default drive strength isn't enough to achieve even
* high-speed mode on EVB board so bump up to 8ma.
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
<6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
<6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
<6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

391
arch/arm/boot/dts/rk628.dtsi
View File

@@ -1,391 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
#include <dt-bindings/reset/rk628-rgu.h>
#include <dt-bindings/clock/rk628-cgu.h>
/ {
rk628_xin_osc0_func: rk628-xin-osc0-func {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "rk628_xin_osc0_func";
};
rk628_xin_osc0_half: rk628-xin-osc0-half {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rk628_xin_osc0_func>;
clock-mult = <1>;
clock-div = <2>;
clock-output-names = "rk628_xin_osc0_half";
};
};
&rk628 {
compatible = "rockchip,rk628";
rk628_cru: cru {
compatible = "rockchip,rk628-cru";
#clock-cells = <1>;
#reset-cells = <1>;
status = "okay";
};
rk628_efuse: efuse {
compatible = "rockchip,rk628-efuse";
clocks = <&rk628_cru CGU_PCLK_EFUSE>;
clock-names = "pclk";
resets = <&rk628_cru RGU_EFUSE>;
#phy-cells = <0>;
status = "disabled";
};
rk628_pinctrl: pinctrl {
compatible = "rockchip,rk628-pinctrl";
status = "okay";
rk628_gpio0: rk628-gpio0 {
clocks = <&rk628_cru CGU_PCLK_GPIO0>;
clock-names = "pclk";
resets = <&rk628_cru RGU_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
rk628_gpio1: rk628-gpio1 {
clocks = <&rk628_cru CGU_PCLK_GPIO1>;
clock-names = "pclk";
resets = <&rk628_cru RGU_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
rk628_gpio2: rk628-gpio2 {
clocks = <&rk628_cru CGU_PCLK_GPIO2>;
clock-names = "pclk";
resets = <&rk628_cru RGU_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
rk628_gpio3: rk628-gpio3 {
clocks = <&rk628_cru CGU_PCLK_GPIO3>;
clock-names = "pclk";
resets = <&rk628_cru RGU_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
rk628_i2sm0_pins: i2sm0 {
pins = "gpio0a2", /* i2sm0_sck */
"gpio0a3", /* i2sm0_lr */
"gpio0a4", /* i2sm0_d0 */
"gpio0a5", /* i2sm0_d1 */
"gpio0a6", /* i2sm0_d2 */
"gpio0a7"; /* i2sm0_d3 */
function = "i2sm0";
};
rk628_hpd_in_pins: hpd-in {
pins = "gpio0b0";
function = "hpd_in";
};
rk628_ddc_tx_pins: ddc-tx {
pins = "gpio0b1", /* ddc_tx_sda */
"gpio0b2"; /* ddc_tx_scl */
function = "ddc_tx";
};
rk628_cec_tx_pins: cec-tx {
pins = "gpio0b3";
function = "cec_tx";
};
rk628_test_clkout_pins: test-clkout {
pins = "gpio1a0";
function = "test_clkout";
};
rk628_i2sm1_pins: i2sm1 {
pins = "gpio1a2", /* i2sm1_sck */
"gpio1a3", /* i2sm1_lr */
"gpio1a4", /* i2sm1_d0 */
"gpio1a5", /* i2sm1_d1 */
"gpio1a6", /* i2sm1_d2 */
"gpio1a7"; /* i2sm1_d3 */
function = "i2sm1";
};
rk628_hpdm0_out_pins: hpdm0-out {
pins = "gpio1b0";
function = "hpdm0_out";
};
rk628_ddcm0_rx_pins: ddcm0-rx {
pins = "gpio1b1", /* ddcm0_rx_sda */
"gpio1b2"; /* ddcm0_rx_scl */
function = "ddcm0_rx";
};
rk628_cecm0_rx_pins: cecm0_rx {
pins = "gpio1b3";
function = "cecm0_rx";
};
rk628_vop_pins: vop {
pins = "gpio2a0", /* vop_d0 */
"gpio2a1", /* vop_d1 */
"gpio2a2", /* vop_d2 */
"gpio2a3", /* vop_d3 */
"gpio2a4", /* vop_d4 */
"gpio2a5", /* vop_d5 */
"gpio2a6", /* vop_d6 */
"gpio2a7", /* vop_d7 */
"gpio2b0", /* vop_d8 */
"gpio2b1", /* vop_d9 */
"gpio2b2", /* vop_d10 */
"gpio2b3", /* vop_d11 */
"gpio2b4", /* vop_d12 */
"gpio2b5", /* vop_d13 */
"gpio2b6", /* vop_d14 */
"gpio2b7", /* vop_d15 */
"gpio2c0", /* vop_d16 */
"gpio2c1", /* vop_d17 */
"gpio2c2", /* vop_d18 */
"gpio2c3", /* vop_d19 */
"gpio2c4", /* vop_d20 */
"gpio2c5", /* vop_d21 */
"gpio2c6", /* vop_d22 */
"gpio2c7", /* vop_d23 */
"gpio3a0", /* vop_den */
"gpio3a1", /* vop_hsync */
"gpio3a3", /* vop_vsync */
"gpio3b0"; /* vop_dclk */
function = "vop";
drive-strength = <1>;
};
rk628_hpdm1_out: hpdm1-out {
pins = "gpio3a4";
function = "hpdm1_out";
};
rk628_ddcm1_rx_pins: ddcm1-rx {
pins = "gpio3a5", /* ddcm1_rx_sda */
"gpio3a6"; /* ddcm1_rx_scl */
function = "ddcm1_rx";
};
rk628_cecm1_rx_pins: cecm1-rx {
pins = "gpio3a7";
function = "cecm1_rx";
};
rk628_gvi_hpd_pins: gvi-hpd {
pins = "gpio3b1";
function = "gvi_hpd";
};
rk628_gvi_lock_pins: gvi-lock {
pins = "gpio3b2";
function = "gvi_lock";
};
rk628_hdmirx_cec0: hdmirx-cec0 {
pins = "hdmirx_cec";
function = "hdmirx_cec0";
};
rk628_hdmirx_cec1: hdmirx-cec1 {
pins = "hdmirx_cec";
function = "hdmirx_cec1";
};
rk628_rxddc_input0: rxddc-input0 {
pins = "rxddc_scl",
"rxddc_sda";
function = "rxddc_input0";
};
rk628_rxddc_input1: rxddc-input1 {
pins = "rxddc_scl",
"rxddc_sda";
function = "rxddc_input1";
};
rk628_i2sm0_input: i2sm0-input {
pins = "i2sm_sck",
"i2sm_d",
"i2sm_lr";
function = "i2sm0_input";
};
rk628_i2sm1_input: i2sm1-input {
pins = "i2sm_sck",
"i2sm_d",
"i2sm_lr";
function = "i2sm1_input";
};
};
rk628_combtxphy: combtxphy {
compatible = "rockchip,rk628-combtxphy";
clocks = <&rk628_cru CGU_PCLK_TXPHY_CON>, <&rk628_cru CGU_SCLK_VOP>;
clock-names = "pclk", "ref_clk";
resets = <&rk628_cru RGU_TXPHY_CON>;
#phy-cells = <0>;
status = "disabled";
};
rk628_combrxphy: combrxphy {
compatible = "rockchip,rk628-combrxphy";
clocks = <&rk628_cru CGU_PCLK_RXPHY>;
clock-names = "pclk";
resets = <&rk628_cru RGU_RXPHY>;
#phy-cells = <0>;
status = "disabled";
};
rk628_dsi0: dsi0 {
compatible = "rockchip,rk628-dsi0";
clocks = <&rk628_cru CGU_PCLK_DSI0>,
<&rk628_cru CGU_CLK_CFG_DPHY0>;
clock-names = "pclk", "cfg";
resets = <&rk628_cru RGU_DSI0>;
phys = <&rk628_combtxphy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rk628_dsi1: dsi1 {
compatible = "rockchip,rk628-dsi1";
clocks = <&rk628_cru CGU_PCLK_DSI1>,
<&rk628_cru CGU_CLK_CFG_DPHY1>;
clock-names = "pclk", "cfg";
resets = <&rk628_cru RGU_DSI1>;
phys = <&rk628_combtxphy>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rk628_lvds: lvds {
compatible = "rockchip,rk628-lvds";
phys = <&rk628_combtxphy>;
status = "disabled";
};
rk628_gvi: gvi {
compatible = "rockchip,rk628-gvi";
clocks = <&rk628_cru CGU_PCLK_GVIHOST>;
clock-names = "pclk";
resets = <&rk628_cru RGU_GVIHOST>;
phys = <&rk628_combtxphy>;
status = "disabled";
};
rk628_rgb_tx: rgb-tx {
compatible = "rockchip,rk628-rgb-tx";
status = "disabled";
};
rk628_yuv_rx: yuv-rx {
compatible = "rockchip,rk628-yuv-rx";
status = "disabled";
};
rk628_yuv_tx: yuv-tx {
compatible = "rockchip,rk628-yuv-tx";
status = "disabled";
};
rk628_bt1120_rx: bt1120-rx {
compatible = "rockchip,rk628-bt1120-rx";
clocks = <&rk628_cru CGU_BT1120DEC>;
clock-names = "bt1120dec";
resets = <&rk628_cru RGU_BT1120DEC>;
status = "disabled";
};
rk628_bt1120_tx: bt1120-tx {
compatible = "rockchip,rk628-bt1120-tx";
status = "disabled";
};
rk628_post_process: post-process {
compatible = "rockchip,rk628-post-process";
clocks = <&rk628_cru CGU_SCLK_VOP>,
<&rk628_cru CGU_CLK_RX_READ>;
clock-names = "sclk_vop", "rx_read";
resets = <&rk628_cru RGU_DECODER>,
<&rk628_cru RGU_CLK_RX>,
<&rk628_cru RGU_VOP>;
reset-names = "decoder", "clk_rx", "vop";
status = "disabled";
};
rk628_hdmi: hdmi {
compatible = "rockchip,rk628-hdmi";
clocks = <&rk628_cru CGU_PCLK_HDMITX>,
<&rk628_cru CGU_SCLK_VOP>;
clock-names = "pclk", "dclk";
pinctrl-names = "default";
pinctrl-0 = <&rk628_hpd_in_pins &rk628_ddc_tx_pins &rk628_i2sm0_pins>;
#sound-dai-cells = <0>;
status = "disabled";
};
rk628_hdmirx: hdmirx {
compatible = "rockchip,rk628-hdmirx";
clocks = <&rk628_cru CGU_PCLK_HDMIRX>,
<&rk628_cru CGU_CLK_HDMIRX_CEC>,
<&rk628_cru CGU_CLK_HDMIRX_AUD>,
<&rk628_cru CGU_CLK_IMODET>;
clock-names = "pclk", "cec", "audio", "imodet";
resets = <&rk628_cru RGU_HDMIRX>,
<&rk628_cru RGU_HDMIRX_PON>;
reset-names = "hdmirx", "hdmirx_pon";
phys = <&rk628_combrxphy>;
status = "disabled";
};
rk628_csi: csi {
compatible = "rockchip,rk628-csi";
clocks = <&rk628_cru CGU_PCLK_HDMIRX>,
<&rk628_cru CGU_CLK_IMODET>,
<&rk628_cru CGU_CLK_HDMIRX_AUD>,
<&rk628_cru CGU_CLK_HDMIRX_CEC>,
<&rk628_cru CGU_SCLK_VOP>,
<&rk628_cru CGU_CLK_RX_READ>,
<&rk628_cru CGU_PCLK_CSI>,
<&rk628_cru CGU_CLK_TESTOUT>;
clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec",
"vop", "rx_read", "csi0", "i2s_mclk";
assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>;
assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>;
resets = <&rk628_cru RGU_HDMIRX>,
<&rk628_cru RGU_HDMIRX_PON>,
<&rk628_cru RGU_DECODER>,
<&rk628_cru RGU_CLK_RX>,
<&rk628_cru RGU_VOP>,
<&rk628_cru RGU_CSI>;
reset-names = "hdmirx", "hdmirx_pon", "decoder", "clk_rx",
"vop", "csi0";
phys = <&rk628_combrxphy>, <&rk628_combtxphy>;
phy-names = "combrxphy", "combtxphy";
pinctrl-names = "default";
pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>;
status = "disabled";
};
};

2
arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts
View File

@@ -76,7 +76,7 @@
&pinctrl {
buttons {
pwr_key: pwr-key {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

4
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -185,10 +185,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb5-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb

12
arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dtsi
View File

@@ -345,13 +345,13 @@
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-suspend-microvolt = <3000000>;
};
};
@@ -396,13 +396,13 @@
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-suspend-microvolt = <3000000>;
};
};

127
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts
View File

@@ -1,127 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#include "rk3568-evb6-ddr3-v10.dtsi"
#include "rk3568-android.dtsi"
&dsi0 {
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
&video_phy0 {
status = "disabled";
};
#include <arm/rk628.dtsi>
&rk628_hdmi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_hdmi>;
};
};
};
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
mode-sync-pol = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_bt1120: endpoint {
remote-endpoint = <&bt1120_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
};
};
};
};
&rk628_bt1120_rx {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bt1120_in_rgb: endpoint {
remote-endpoint = <&rgb_out_bt1120>;
};
};
port@1 {
reg = <1>;
bt1120_out_post_process: endpoint {
remote-endpoint = <&post_process_in_bt1120>;
};
};
};
};
&rgb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bt1120_pins>;
ports {
port@1 {
reg = <1>;
rgb_out_bt1120: endpoint {
remote-endpoint = <&bt1120_in_rgb>;
};
};
};
};
&rgb_in_vp2 {
status = "okay";
};
&vcc3v3_lcd1_n {
status = "disabled";
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

419
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts
View File

@@ -1,419 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#include "rk3568-evb6-ddr3-v10.dtsi"
#include "rk3568-android.dtsi"
&dsi0 {
status = "disabled";
};
&video_phy0 {
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
#include <arm/rk628.dtsi>
&backlight {
pwms = <&pwm14 0 25000 0>;
};
&pwm14 {
status = "okay";
};
&rk628_dsi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in_post_process: endpoint {
remote-endpoint = <&post_process_out_dsi0>;
};
};
};
panel@0 {
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
init-delay-ms = <120>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM |
MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
23 00 02 FE 21
23 00 02 04 00
23 00 02 00 64
23 00 02 2A 00
23 00 02 26 64
23 00 02 54 00
23 00 02 50 64
23 00 02 7B 00
23 00 02 77 64
23 00 02 A2 00
23 00 02 9D 64
23 00 02 C9 00
23 00 02 C5 64
23 00 02 01 71
23 00 02 27 71
23 00 02 51 71
23 00 02 78 71
23 00 02 9E 71
23 00 02 C6 71
23 00 02 02 89
23 00 02 28 89
23 00 02 52 89
23 00 02 79 89
23 00 02 9F 89
23 00 02 C7 89
23 00 02 03 9E
23 00 02 29 9E
23 00 02 53 9E
23 00 02 7A 9E
23 00 02 A0 9E
23 00 02 C8 9E
23 00 02 09 00
23 00 02 05 B0
23 00 02 31 00
23 00 02 2B B0
23 00 02 5A 00
23 00 02 55 B0
23 00 02 80 00
23 00 02 7C B0
23 00 02 A7 00
23 00 02 A3 B0
23 00 02 CE 00
23 00 02 CA B0
23 00 02 06 C0
23 00 02 2D C0
23 00 02 56 C0
23 00 02 7D C0
23 00 02 A4 C0
23 00 02 CB C0
23 00 02 07 CF
23 00 02 2F CF
23 00 02 58 CF
23 00 02 7E CF
23 00 02 A5 CF
23 00 02 CC CF
23 00 02 08 DD
23 00 02 30 DD
23 00 02 59 DD
23 00 02 7F DD
23 00 02 A6 DD
23 00 02 CD DD
23 00 02 0E 15
23 00 02 0A E9
23 00 02 36 15
23 00 02 32 E9
23 00 02 5F 15
23 00 02 5B E9
23 00 02 85 15
23 00 02 81 E9
23 00 02 AD 15
23 00 02 A9 E9
23 00 02 D3 15
23 00 02 CF E9
23 00 02 0B 14
23 00 02 33 14
23 00 02 5C 14
23 00 02 82 14
23 00 02 AA 14
23 00 02 D0 14
23 00 02 0C 36
23 00 02 34 36
23 00 02 5D 36
23 00 02 83 36
23 00 02 AB 36
23 00 02 D1 36
23 00 02 0D 6B
23 00 02 35 6B
23 00 02 5E 6B
23 00 02 84 6B
23 00 02 AC 6B
23 00 02 D2 6B
23 00 02 13 5A
23 00 02 0F 94
23 00 02 3B 5A
23 00 02 37 94
23 00 02 64 5A
23 00 02 60 94
23 00 02 8A 5A
23 00 02 86 94
23 00 02 B2 5A
23 00 02 AE 94
23 00 02 D8 5A
23 00 02 D4 94
23 00 02 10 D1
23 00 02 38 D1
23 00 02 61 D1
23 00 02 87 D1
23 00 02 AF D1
23 00 02 D5 D1
23 00 02 11 04
23 00 02 39 04
23 00 02 62 04
23 00 02 88 04
23 00 02 B0 04
23 00 02 D6 04
23 00 02 12 05
23 00 02 3A 05
23 00 02 63 05
23 00 02 89 05
23 00 02 B1 05
23 00 02 D7 05
23 00 02 18 AA
23 00 02 14 36
23 00 02 42 AA
23 00 02 3D 36
23 00 02 69 AA
23 00 02 65 36
23 00 02 8F AA
23 00 02 8B 36
23 00 02 B7 AA
23 00 02 B3 36
23 00 02 DD AA
23 00 02 D9 36
23 00 02 15 74
23 00 02 3F 74
23 00 02 66 74
23 00 02 8C 74
23 00 02 B4 74
23 00 02 DA 74
23 00 02 16 9F
23 00 02 40 9F
23 00 02 67 9F
23 00 02 8D 9F
23 00 02 B5 9F
23 00 02 DB 9F
23 00 02 17 DC
23 00 02 41 DC
23 00 02 68 DC
23 00 02 8E DC
23 00 02 B6 DC
23 00 02 DC DC
23 00 02 1D FF
23 00 02 19 03
23 00 02 47 FF
23 00 02 43 03
23 00 02 6E FF
23 00 02 6A 03
23 00 02 94 FF
23 00 02 90 03
23 00 02 BC FF
23 00 02 B8 03
23 00 02 E2 FF
23 00 02 DE 03
23 00 02 1A 35
23 00 02 44 35
23 00 02 6B 35
23 00 02 91 35
23 00 02 B9 35
23 00 02 DF 35
23 00 02 1B 45
23 00 02 45 45
23 00 02 6C 45
23 00 02 92 45
23 00 02 BA 45
23 00 02 E0 45
23 00 02 1C 55
23 00 02 46 55
23 00 02 6D 55
23 00 02 93 55
23 00 02 BB 55
23 00 02 E1 55
23 00 02 22 FF
23 00 02 1E 68
23 00 02 4C FF
23 00 02 48 68
23 00 02 73 FF
23 00 02 6F 68
23 00 02 99 FF
23 00 02 95 68
23 00 02 C1 FF
23 00 02 BD 68
23 00 02 E7 FF
23 00 02 E3 68
23 00 02 1F 7E
23 00 02 49 7E
23 00 02 70 7E
23 00 02 96 7E
23 00 02 BE 7E
23 00 02 E4 7E
23 00 02 20 97
23 00 02 4A 97
23 00 02 71 97
23 00 02 97 97
23 00 02 BF 97
23 00 02 E5 97
23 00 02 21 B5
23 00 02 4B B5
23 00 02 72 B5
23 00 02 98 B5
23 00 02 C0 B5
23 00 02 E6 B5
23 00 02 25 F0
23 00 02 23 E8
23 00 02 4F F0
23 00 02 4D E8
23 00 02 76 F0
23 00 02 74 E8
23 00 02 9C F0
23 00 02 9A E8
23 00 02 C4 F0
23 00 02 C2 E8
23 00 02 EA F0
23 00 02 E8 E8
23 00 02 24 FF
23 00 02 4E FF
23 00 02 75 FF
23 00 02 9B FF
23 00 02 C3 FF
23 00 02 E9 FF
23 00 02 FE 3D
23 00 02 00 04
23 00 02 FE 23
23 00 02 08 82
23 00 02 0A 00
23 00 02 0B 00
23 00 02 0C 01
23 00 02 16 00
23 00 02 18 02
23 00 02 1B 04
23 00 02 19 04
23 00 02 1C 81
23 00 02 1F 00
23 00 02 20 03
23 00 02 23 04
23 00 02 21 01
23 00 02 54 63
23 00 02 55 54
23 00 02 6E 45
23 00 02 6D 36
23 00 02 FE 3D
23 00 02 55 78
23 00 02 FE 20
23 00 02 26 30
23 00 02 FE 3D
23 00 02 20 71
23 00 02 50 8F
23 00 02 51 8F
23 00 02 FE 00
23 00 02 35 00
05 78 01 11
05 1E 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
disp_timings3: display-timings {
native-mode = <&dsi0_timing3>;
dsi0_timing3: timing0 {
clock-frequency = <132000000>;
hactive = <1080>;
vactive = <1920>;
hfront-porch = <15>;
hsync-len = <2>;
hback-porch = <30>;
vfront-porch = <15>;
vsync-len = <2>;
vback-porch = <15>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
};
};
&rk628_combtxphy {
status = "okay";
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
mode-sync-pol = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&rgb_in_vp2 {
status = "okay";
};
&vcc3v3_lcd1_n {
status = "disabled";
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

96
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts
View File

@@ -1,96 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#include "rk3568-evb6-ddr3-v10.dtsi"
#include "rk3568-android.dtsi"
&dsi0 {
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
#include <arm/rk628.dtsi>
&rk628_hdmi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_hdmi>;
};
};
};
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
mode-sync-pol = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&rgb_in_vp2 {
status = "okay";
};
&vcc3v3_lcd1_n {
status = "disabled";
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

173
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts
View File

@@ -1,173 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/display/media-bus-format.h>
#include "rk3568-evb6-ddr3-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
vcc33_lcd: vcc33-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc33_lcd";
regulator-boot-on;
regulator-always-on;
gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
panel {
compatible = "simple-panel";
power-supply = <&vcc33_lcd>;
backlight = <&backlight>;
enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <66600000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <30>;
hfront-porch = <30>;
vback-porch = <3>;
vfront-porch = <3>;
hsync-len = <4>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
};
&dsi0 {
status = "disabled";
};
&video_phy0 {
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
#include <arm/rk628.dtsi>
&backlight {
pwms = <&pwm14 0 25000 0>;
};
&pwm14 {
status = "okay";
};
&rk628_lvds {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_post_process: endpoint {
remote-endpoint = <&post_process_out_lvds>;
};
};
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&rk628_combtxphy {
status = "okay";
};
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&rk628_vop_pins>;
status = "okay";
mode-sync-pol = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
};
};
port@1 {
reg = <1>;
post_process_out_lvds: endpoint {
remote-endpoint = <&lvds_in_post_process>;
};
};
};
};
&rgb {
status = "okay";
ports {
port@1 {
reg = <1>;
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
};
};
};
};
&rgb_in_vp2 {
status = "okay";
};
&vcc3v3_lcd1_n {
status = "disabled";
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&gmac1 {
status = "disabled";
};

9
arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi
View File

@@ -5,14 +5,6 @@
*/
/ {
cam_ircut0: cam_ircut {
status = "okay";
compatible = "rockchip,ircut";
ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
vcc_mipidphy0: vcc-mipidcphy0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
@@ -74,7 +66,6 @@
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
lens-focus = <&cam_ircut0>;
port {
imx415_out0: endpoint {
remote-endpoint = <&mipidphy0_in_ucam0>;

2
arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi
View File

@@ -130,7 +130,7 @@
};
&display_subsystem {
clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi0>;
clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>;
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
};

4
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
View File

@@ -349,6 +349,10 @@
vin-supply = <&dphy3_vcc12v_buck>;
};
&max96712_dphy3 {
lock-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
};
&max96756_dphy0_vcc1v2 {
vin-supply = <&vcc5v0_buck>;
};

160
arch/arm64/configs/rk3588_vehicle.config Normal file
View File

@@ -0,0 +1,160 @@
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_CW2017 is not set
# CONFIG_BATTERY_CW221X is not set
# CONFIG_BATTERY_RK817 is not set
# CONFIG_BATTERY_RK818 is not set
# CONFIG_CHARGER_BQ25700 is not set
# CONFIG_CHARGER_BQ25890 is not set
# CONFIG_CHARGER_RK817 is not set
# CONFIG_CHARGER_RK818 is not set
# CONFIG_CHARGER_SC8551 is not set
# CONFIG_CHARGER_SC89890 is not set
# CONFIG_CHARGER_SGM41542 is not set
# CONFIG_COMMON_CLK_PWM is not set
# CONFIG_COMPASS_DEVICE is not set
# CONFIG_CPU_IDLE_GOV_MENU is not set
CONFIG_CPU_IDLE_GOV_TEO=y
# CONFIG_CPU_PX30 is not set
# CONFIG_CPU_RK3328 is not set
# CONFIG_CPU_RK3368 is not set
# CONFIG_CPU_RK3399 is not set
# CONFIG_CPU_RK3528 is not set
# CONFIG_CPU_RK3562 is not set
# CONFIG_CPU_RK3568 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_V3 is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_RK1000_TVE is not set
# CONFIG_DRM_RK630_TVE is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
CONFIG_GPIO_NCA9539=y
# CONFIG_HALL_DEVICE is not set
CONFIG_HZ=1000
CONFIG_HZ_1000=y
# CONFIG_HZ_300 is not set
# CONFIG_IIO_ST_LSM6DSR is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_LIGHT_DEVICE is not set
CONFIG_LOG_BUF_SHIFT=18
# CONFIG_MALI400 is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MFD_RK618 is not set
# CONFIG_MFD_RK628 is not set
# CONFIG_MFD_RK630_I2C is not set
# CONFIG_MFD_RKX110_X120 is not set
CONFIG_MFD_SERDES_DISPLAY=y
# CONFIG_PROXIMITY_DEVICE is not set
# CONFIG_R8168 is not set
CONFIG_REALTEK_PHY=y
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_REGULATOR_LP8752 is not set
# CONFIG_REGULATOR_MP8865 is not set
# CONFIG_REGULATOR_TPS65132 is not set
# CONFIG_REGULATOR_WL2868C is not set
# CONFIG_REGULATOR_XZ3216 is not set
# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set
# CONFIG_ROCKCHIP_CLK_BOOST is not set
# CONFIG_ROCKCHIP_CLK_INV is not set
# CONFIG_ROCKCHIP_CLK_PVTM is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
# CONFIG_ROCKCHIP_VOP is not set
CONFIG_SATA_AHCI_PLATFORM=m
# CONFIG_SLUB_SYSFS is not set
# CONFIG_SND_SOC_AW883XX is not set
# CONFIG_SND_SOC_CX2072X is not set
# CONFIG_SND_SOC_ES8311 is not set
# CONFIG_SND_SOC_ES8316 is not set
# CONFIG_SND_SOC_ES8326 is not set
# CONFIG_SND_SOC_ES8396 is not set
# CONFIG_SND_SOC_RK3328 is not set
# CONFIG_SND_SOC_RK3528 is not set
# CONFIG_SND_SOC_RK817 is not set
# CONFIG_SND_SOC_RK_CODEC_DIGITAL is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
CONFIG_TOUCHSCREEN_GT1X=m
CONFIG_TOUCHSCREEN_HIMAX_CHIPSET=y
CONFIG_TOUCHSCREEN_ILI210X=m
# CONFIG_UCS12CM0 is not set
# CONFIG_USB_ALI_M5632 is not set
# CONFIG_USB_AN2720 is not set
# CONFIG_USB_EPSON2888 is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_KC2190 is not set
# CONFIG_USB_NET_CX82310_ETH is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_GL620A is not set
# CONFIG_USB_NET_INT51X1 is not set
# CONFIG_USB_NET_MCS7830 is not set
# CONFIG_USB_NET_SMSC75XX is not set
# CONFIG_USB_NET_SMSC95XX is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
# CONFIG_VIDEO_AW36518 is not set
# CONFIG_VIDEO_AW8601 is not set
# CONFIG_VIDEO_CN3927V is not set
# CONFIG_VIDEO_DW9714 is not set
# CONFIG_VIDEO_FP5510 is not set
# CONFIG_VIDEO_GC2145 is not set
# CONFIG_VIDEO_GC2385 is not set
# CONFIG_VIDEO_GC4C33 is not set
# CONFIG_VIDEO_GC8034 is not set
# CONFIG_VIDEO_IMX415 is not set
CONFIG_VIDEO_MAXIM_SERDES=y
# CONFIG_VIDEO_OV02B10 is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV13855 is not set
# CONFIG_VIDEO_OV50C40 is not set
# CONFIG_VIDEO_OV5695 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_RK628_BT1120 is not set
# CONFIG_VIDEO_RK628_CSI is not set
# CONFIG_VIDEO_RK_IRCUT is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21 is not set
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32 is not set
# CONFIG_VIDEO_S5K3L6XX is not set
# CONFIG_VIDEO_S5KJN1 is not set
# CONFIG_VIDEO_SGM3784 is not set
# CONFIG_VL6180 is not set
# CONFIG_ROCKCHIP_DRM_SELF_TEST is not set
CONFIG_SERDES_DISPLAY_CHIP_MAXIM=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96745=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96752=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96755=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96772=y
CONFIG_SERDES_DISPLAY_CHIP_MAXIM_MAX96789=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO=y
CONFIG_SERDES_DISPLAY_CHIP_NOVO_NCA9539=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX111=y
CONFIG_SERDES_DISPLAY_CHIP_ROCKCHIP_RKX121=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
CONFIG_TOUCHSCREEN_HIMAX_COMMON=m
CONFIG_TOUCHSCREEN_HIMAX_DEBUG=y
# CONFIG_TOUCHSCREEN_HIMAX_EMBEDDED_FIRMWARE is not set
# CONFIG_TOUCHSCREEN_HIMAX_IC_HX83191 is not set
CONFIG_TOUCHSCREEN_HIMAX_IC_HX83192=m
# CONFIG_TOUCHSCREEN_HIMAX_IC_HX83193 is not set
CONFIG_TOUCHSCREEN_HIMAX_INCELL=y
# CONFIG_TOUCHSCREEN_HIMAX_INSPECT is not set
CONFIG_VIDEO_MAXIM_CAM_OV231X=y
CONFIG_VIDEO_MAXIM_CAM_OX01F10=y
CONFIG_VIDEO_MAXIM_CAM_OX03J10=y
CONFIG_VIDEO_MAXIM_CAM_SC320AT=y
CONFIG_VIDEO_MAXIM_DES_MAXIM4C=y
CONFIG_VIDEO_MAXIM_SER_MAX9295=y
CONFIG_VIDEO_MAXIM_SER_MAX96715=y
CONFIG_VIDEO_MAXIM_SER_MAX96717=y

6
drivers/clk/rockchip/regmap/Kconfig
View File

@@ -8,9 +8,3 @@ config CLK_RK618
depends on MFD_RK618
default MFD_RK618
select COMMON_CLK_ROCKCHIP_REGMAP
config CLK_RK628
tristate "Clock driver for Rockchip RK628"
depends on MFD_RK628
default MFD_RK628
select COMMON_CLK_ROCKCHIP_REGMAP

1
drivers/clk/rockchip/regmap/Makefile
View File

@@ -10,4 +10,3 @@ clk-rockchip-regmap-objs := clk-regmap-mux.o \
clk-regmap-pll.o
obj-$(CONFIG_CLK_RK618) += clk-rk618.o
obj-$(CONFIG_CLK_RK628) += clk-rk628.o

31
drivers/clk/rockchip/regmap/clk-regmap.h
View File

@@ -154,23 +154,6 @@ struct clk_composite_data {
.flags = _flags, \
}
#define COMPOSITE_NOMUX(_id, _name, _parent_name, \
_div_reg, _div_shift, _div_width, \
_gate_reg, _gate_shift, _flags) \
{ \
.id = _id, \
.name = _name, \
.parent_names = (const char *[]){ _parent_name }, \
.num_parents = 1, \
.div_reg = _div_reg, \
.div_shift = _div_shift, \
.div_width = _div_width, \
.div_flags = CLK_DIVIDER_HIWORD_MASK, \
.gate_reg = _gate_reg, \
.gate_shift = _gate_shift, \
.flags = _flags, \
}
#define COMPOSITE_NODIV(_id, _name, _parent_names, \
_mux_reg, _mux_shift, _mux_width, \
_gate_reg, _gate_shift, _flags) \
@@ -197,20 +180,6 @@ struct clk_composite_data {
.flags = _flags, \
}
#define COMPOSITE_FRAC_NOMUX(_id, _name, _parent_name, \
_div_reg, \
_gate_reg, _gate_shift, _flags) \
{ \
.id = _id, \
.name = _name, \
.parent_names = (const char *[]){ _parent_name }, \
.num_parents = 1, \
.div_reg = _div_reg, \
.gate_reg = _gate_reg, \
.gate_shift = _gate_shift, \
.flags = _flags, \
}
#define COMPOSITE_FRAC_NOGATE(_id, _name, _parent_names, \
_mux_reg, _mux_shift, _mux_width, \
_div_reg, \

609
drivers/clk/rockchip/regmap/clk-rk628.c
View File

@@ -1,609 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/mfd/rk628.h>
#include <dt-bindings/reset/rk628-rgu.h>
#include <dt-bindings/clock/rk628-cgu.h>
#include "clk-regmap.h"
#define RK628_PLL(_id, _name, _parent_name, _reg, _flags) \
PLL(_id, _name, _parent_name, _reg, 13, 12, 10, _flags)
#define REG(x) ((x) + 0xc0000)
#define CRU_CPLL_CON0 REG(0x0000)
#define CRU_CPLL_CON1 REG(0x0004)
#define CRU_CPLL_CON2 REG(0x0008)
#define CRU_CPLL_CON3 REG(0x000c)
#define CRU_CPLL_CON4 REG(0x0010)
#define CRU_GPLL_CON0 REG(0x0020)
#define CRU_GPLL_CON1 REG(0x0024)
#define CRU_GPLL_CON2 REG(0x0028)
#define CRU_GPLL_CON3 REG(0x002c)
#define CRU_GPLL_CON4 REG(0x0030)
#define CRU_MODE_CON REG(0x0060)
#define CRU_CLKSEL_CON00 REG(0x0080)
#define CRU_CLKSEL_CON01 REG(0x0084)
#define CRU_CLKSEL_CON02 REG(0x0088)
#define CRU_CLKSEL_CON03 REG(0x008c)
#define CRU_CLKSEL_CON04 REG(0x0090)
#define CRU_CLKSEL_CON05 REG(0x0094)
#define CRU_CLKSEL_CON06 REG(0x0098)
#define CRU_CLKSEL_CON07 REG(0x009c)
#define CRU_CLKSEL_CON08 REG(0x00a0)
#define CRU_CLKSEL_CON09 REG(0x00a4)
#define CRU_CLKSEL_CON10 REG(0x00a8)
#define CRU_CLKSEL_CON11 REG(0x00ac)
#define CRU_CLKSEL_CON12 REG(0x00b0)
#define CRU_CLKSEL_CON13 REG(0x00b4)
#define CRU_CLKSEL_CON14 REG(0x00b8)
#define CRU_CLKSEL_CON15 REG(0x00bc)
#define CRU_CLKSEL_CON16 REG(0x00c0)
#define CRU_CLKSEL_CON17 REG(0x00c4)
#define CRU_CLKSEL_CON18 REG(0x00c8)
#define CRU_CLKSEL_CON20 REG(0x00d0)
#define CRU_CLKSEL_CON21 REG(0x00d4)
#define CRU_GATE_CON00 REG(0x0180)
#define CRU_GATE_CON01 REG(0x0184)
#define CRU_GATE_CON02 REG(0x0188)
#define CRU_GATE_CON03 REG(0x018c)
#define CRU_GATE_CON04 REG(0x0190)
#define CRU_GATE_CON05 REG(0x0194)
#define CRU_SOFTRST_CON00 REG(0x0200)
#define CRU_SOFTRST_CON01 REG(0x0204)
#define CRU_SOFTRST_CON02 REG(0x0208)
#define CRU_SOFTRST_CON04 REG(0x0210)
#define CRU_MAX_REGISTER CRU_SOFTRST_CON04
#define reset_to_cru(_rst) container_of(_rst, struct rk628_cru, rcdev)
struct rk628_cru {
struct device *dev;
struct rk628 *parent;
struct regmap *regmap;
struct reset_controller_dev rcdev;
struct clk_onecell_data clk_data;
};
#define CNAME(x) "rk628_" x
#define PNAME(x) static const char *const x[]
PNAME(mux_cpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_cpll") };
PNAME(mux_gpll_osc_p) = { CNAME("xin_osc0_func"), CNAME("clk_gpll") };
PNAME(mux_cpll_gpll_mux_p) = { CNAME("clk_cpll_mux"), CNAME("clk_gpll_mux") };
PNAME(mux_mclk_i2s_8ch_p) = { CNAME("clk_i2s_8ch_src"),
CNAME("clk_i2s_8ch_frac"), CNAME("i2s_mclkin"),
CNAME("xin_osc0_half") };
PNAME(mux_i2s_mclkout_p) = { CNAME("mclk_i2s_8ch"), CNAME("xin_osc0_half") };
PNAME(mux_clk_testout_p) = { CNAME("xin_osc0_func"), CNAME("xin_osc0_half"),
CNAME("clk_gpll"), CNAME("clk_gpll_mux"),
CNAME("clk_cpll"), CNAME("clk_gpll_mux"),
CNAME("pclk_logic"), CNAME("sclk_vop"),
CNAME("mclk_i2s_8ch"), CNAME("i2s_mclkout"),
CNAME("dummy"), CNAME("clk_hdmirx_aud"),
CNAME("clk_hdmirx_cec"), CNAME("clk_imodet"),
CNAME("clk_txesc"), CNAME("clk_gpio_db0") };
static const struct clk_pll_data rk628_clk_plls[] = {
RK628_PLL(CGU_CLK_CPLL, CNAME("clk_cpll"), CNAME("xin_osc0_func"),
CRU_CPLL_CON0,
0),
RK628_PLL(CGU_CLK_GPLL, CNAME("clk_gpll"), CNAME("xin_osc0_func"),
CRU_GPLL_CON0,
0),
};
static const struct clk_mux_data rk628_clk_muxes[] = {
MUX(CGU_CLK_CPLL_MUX, CNAME("clk_cpll_mux"), mux_cpll_osc_p,
CRU_MODE_CON, 0, 1,
0),
MUX(CGU_CLK_GPLL_MUX, CNAME("clk_gpll_mux"), mux_gpll_osc_p,
CRU_MODE_CON, 2, 1,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
};
static const struct clk_gate_data rk628_clk_gates[] = {
GATE(CGU_PCLK_GPIO0, CNAME("pclk_gpio0"), CNAME("pclk_logic"),
CRU_GATE_CON01, 0,
0),
GATE(CGU_PCLK_GPIO1, CNAME("pclk_gpio1"), CNAME("pclk_logic"),
CRU_GATE_CON01, 1,
0),
GATE(CGU_PCLK_GPIO2, CNAME("pclk_gpio2"), CNAME("pclk_logic"),
CRU_GATE_CON01, 2,
0),
GATE(CGU_PCLK_GPIO3, CNAME("pclk_gpio3"), CNAME("pclk_logic"),
CRU_GATE_CON01, 3,
0),
GATE(CGU_PCLK_TXPHY_CON, CNAME("pclk_txphy_con"), CNAME("pclk_logic"),
CRU_GATE_CON02, 3,
CLK_IGNORE_UNUSED),
GATE(CGU_PCLK_EFUSE, CNAME("pclk_efuse"), CNAME("pclk_logic"),
CRU_GATE_CON00, 5,
0),
GATE(0, CNAME("pclk_i2c2apb"), CNAME("pclk_logic"),
CRU_GATE_CON00, 3,
CLK_IGNORE_UNUSED),
GATE(0, CNAME("pclk_cru"), CNAME("pclk_logic"),
CRU_GATE_CON00, 1,
CLK_IGNORE_UNUSED),
GATE(0, CNAME("pclk_adapter"), CNAME("pclk_logic"),
CRU_GATE_CON00, 7,
CLK_IGNORE_UNUSED),
GATE(0, CNAME("pclk_regfile"), CNAME("pclk_logic"),
CRU_GATE_CON00, 2,
CLK_IGNORE_UNUSED),
GATE(CGU_PCLK_DSI0, CNAME("pclk_dsi0"), CNAME("pclk_logic"),
CRU_GATE_CON02, 6,
0),
GATE(CGU_PCLK_DSI1, CNAME("pclk_dsi1"), CNAME("pclk_logic"),
CRU_GATE_CON02, 7,
0),
GATE(CGU_PCLK_CSI, CNAME("pclk_csi"), CNAME("pclk_logic"),
CRU_GATE_CON02, 8,
0),
GATE(CGU_PCLK_HDMITX, CNAME("pclk_hdmitx"), CNAME("pclk_logic"),
CRU_GATE_CON02, 4,
0),
GATE(CGU_PCLK_RXPHY, CNAME("pclk_rxphy"), CNAME("pclk_logic"),
CRU_GATE_CON02, 0,
0),
GATE(CGU_PCLK_HDMIRX, CNAME("pclk_hdmirx"), CNAME("pclk_logic"),
CRU_GATE_CON02, 2,
0),
GATE(CGU_PCLK_GVIHOST, CNAME("pclk_gvihost"), CNAME("pclk_logic"),
CRU_GATE_CON02, 5,
0),
GATE(CGU_CLK_CFG_DPHY0, CNAME("clk_cfg_dphy0"), CNAME("xin_osc0_func"),
CRU_GATE_CON02, 13,
0),
GATE(CGU_CLK_CFG_DPHY1, CNAME("clk_cfg_dphy1"), CNAME("xin_osc0_func"),
CRU_GATE_CON02, 14,
0),
GATE(CGU_CLK_TXESC, CNAME("clk_txesc"), CNAME("xin_osc0_func"),
CRU_GATE_CON02, 12,
0),
};
static const struct clk_composite_data rk628_clk_composites[] = {
COMPOSITE(CGU_CLK_IMODET, CNAME("clk_imodet"), mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON05, 5, 1,
CRU_CLKSEL_CON05, 0, 5,
CRU_GATE_CON02, 11,
0),
COMPOSITE(CGU_CLK_HDMIRX_AUD, CNAME("clk_hdmirx_aud"),
mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON05, 15, 1,
CRU_CLKSEL_CON05, 6, 8,
CRU_GATE_CON02, 10,
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
COMPOSITE_FRAC_NOMUX(CGU_CLK_HDMIRX_CEC, CNAME("clk_hdmirx_cec"),
CNAME("xin_osc0_func"),
CRU_CLKSEL_CON12,
CRU_GATE_CON01, 15,
0),
COMPOSITE_FRAC(CGU_CLK_RX_READ, CNAME("clk_rx_read"),
mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON02, 8, 1,
CRU_CLKSEL_CON14,
CRU_GATE_CON00, 11,
0),
COMPOSITE_FRAC(CGU_SCLK_VOP, CNAME("sclk_vop"), mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON02, 9, 1,
CRU_CLKSEL_CON13,
CRU_GATE_CON00, 13,
CLK_SET_RATE_NO_REPARENT),
COMPOSITE(CGU_PCLK_LOGIC, CNAME("pclk_logic"), mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON00, 7, 1,
CRU_CLKSEL_CON00, 0, 5,
CRU_GATE_CON00, 0,
0),
COMPOSITE_NOMUX(CGU_CLK_GPIO_DB0, CNAME("clk_gpio_db0"),
CNAME("xin_osc0_func"),
CRU_CLKSEL_CON08, 0, 10,
CRU_GATE_CON01, 4,
0),
COMPOSITE_NOMUX(CGU_CLK_GPIO_DB1, CNAME("clk_gpio_db1"),
CNAME("xin_osc0_func"),
CRU_CLKSEL_CON09, 0, 10,
CRU_GATE_CON01, 5,
0),
COMPOSITE_NOMUX(CGU_CLK_GPIO_DB2, CNAME("clk_gpio_db2"),
CNAME("xin_osc0_func"),
CRU_CLKSEL_CON10, 0, 10,
CRU_GATE_CON01, 6,
0),
COMPOSITE_NOMUX(CGU_CLK_GPIO_DB3, CNAME("clk_gpio_db3"),
CNAME("xin_osc0_func"),
CRU_CLKSEL_CON11, 0, 10,
CRU_GATE_CON01, 7,
0),
COMPOSITE(CGU_CLK_I2S_8CH_SRC, CNAME("clk_i2s_8ch_src"),
mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON03, 13, 1,
CRU_CLKSEL_CON03, 8, 5,
CRU_GATE_CON03, 9,
0),
COMPOSITE_FRAC_NOMUX(CGU_CLK_I2S_8CH_FRAC, CNAME("clk_i2s_8ch_frac"),
CNAME("clk_i2s_8ch_src"),
CRU_CLKSEL_CON04,
CRU_GATE_CON03, 10,
0),
COMPOSITE_NODIV(CGU_MCLK_I2S_8CH, CNAME("mclk_i2s_8ch"),
mux_mclk_i2s_8ch_p,
CRU_CLKSEL_CON03, 14, 2,
CRU_GATE_CON03, 11,
CLK_SET_RATE_PARENT),
COMPOSITE_NODIV(CGU_I2S_MCLKOUT, CNAME("i2s_mclkout"),
mux_i2s_mclkout_p,
CRU_CLKSEL_CON03, 7, 1,
CRU_GATE_CON03, 12,
CLK_SET_RATE_PARENT),
COMPOSITE(CGU_BT1120DEC, CNAME("clk_bt1120dec"), mux_cpll_gpll_mux_p,
CRU_CLKSEL_CON02, 7, 1,
CRU_CLKSEL_CON02, 0, 5,
CRU_GATE_CON00, 12,
0),
COMPOSITE(CGU_CLK_TESTOUT, CNAME("clk_testout"), mux_clk_testout_p,
CRU_CLKSEL_CON06, 0, 4,
CRU_CLKSEL_CON06, 8, 6,
CRU_GATE_CON04, 7,
0),
};
static void rk628_clk_add_lookup(struct rk628_cru *cru, struct clk *clk,
unsigned int id)
{
if (cru->clk_data.clks && id)
cru->clk_data.clks[id] = clk;
}
static void rk628_clk_register_muxes(struct rk628_cru *cru)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rk628_clk_muxes); i++) {
const struct clk_mux_data *data = &rk628_clk_muxes[i];
clk = devm_clk_regmap_register_mux(cru->dev, data->name,
data->parent_names,
data->num_parents,
cru->regmap, data->reg,
data->shift, data->width,
data->flags);
if (IS_ERR(clk)) {
dev_err(cru->dev, "failed to register clock %s\n",
data->name);
continue;
}
rk628_clk_add_lookup(cru, clk, data->id);
}
}
static void rk628_clk_register_gates(struct rk628_cru *cru)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rk628_clk_gates); i++) {
const struct clk_gate_data *data = &rk628_clk_gates[i];
clk = devm_clk_regmap_register_gate(cru->dev, data->name,
data->parent_name,
cru->regmap,
data->reg, data->shift,
data->flags);
if (IS_ERR(clk)) {
dev_err(cru->dev, "failed to register clock %s\n",
data->name);
continue;
}
rk628_clk_add_lookup(cru, clk, data->id);
}
}
static void rk628_clk_register_composites(struct rk628_cru *cru)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rk628_clk_composites); i++) {
const struct clk_composite_data *data =
&rk628_clk_composites[i];
clk = devm_clk_regmap_register_composite(cru->dev, data->name,
data->parent_names,
data->num_parents,
cru->regmap,
data->mux_reg,
data->mux_shift,
data->mux_width,
data->div_reg,
data->div_shift,
data->div_width,
data->div_flags,
data->gate_reg,
data->gate_shift,
data->flags);
if (IS_ERR(clk)) {
dev_err(cru->dev, "failed to register clock %s\n",
data->name);
continue;
}
rk628_clk_add_lookup(cru, clk, data->id);
}
}
static void rk628_clk_register_plls(struct rk628_cru *cru)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rk628_clk_plls); i++) {
const struct clk_pll_data *data = &rk628_clk_plls[i];
clk = devm_clk_regmap_register_pll(cru->dev, data->name,
data->parent_name,
cru->regmap,
data->reg,
data->pd_shift,
data->dsmpd_shift,
data->lock_shift,
data->flags);
if (IS_ERR(clk)) {
dev_err(cru->dev, "failed to register clock %s\n",
data->name);
continue;
}
rk628_clk_add_lookup(cru, clk, data->id);
}
}
struct rk628_rgu_data {
unsigned int id;
unsigned int reg;
unsigned int bit;
};
#define RSTGEN(_id, _reg, _bit) \
{ \
.id = (_id), \
.reg = (_reg), \
.bit = (_bit), \
}
static const struct rk628_rgu_data rk628_rgu_data[] = {
RSTGEN(RGU_LOGIC, CRU_SOFTRST_CON00, 0),
RSTGEN(RGU_CRU, CRU_SOFTRST_CON00, 1),
RSTGEN(RGU_REGFILE, CRU_SOFTRST_CON00, 2),
RSTGEN(RGU_I2C2APB, CRU_SOFTRST_CON00, 3),
RSTGEN(RGU_EFUSE, CRU_SOFTRST_CON00, 5),
RSTGEN(RGU_ADAPTER, CRU_SOFTRST_CON00, 7),
RSTGEN(RGU_CLK_RX, CRU_SOFTRST_CON00, 11),
RSTGEN(RGU_BT1120DEC, CRU_SOFTRST_CON00, 12),
RSTGEN(RGU_VOP, CRU_SOFTRST_CON00, 13),
RSTGEN(RGU_GPIO0, CRU_SOFTRST_CON01, 0),
RSTGEN(RGU_GPIO1, CRU_SOFTRST_CON01, 1),
RSTGEN(RGU_GPIO2, CRU_SOFTRST_CON01, 2),
RSTGEN(RGU_GPIO3, CRU_SOFTRST_CON01, 3),
RSTGEN(RGU_GPIO_DB0, CRU_SOFTRST_CON01, 4),
RSTGEN(RGU_GPIO_DB1, CRU_SOFTRST_CON01, 5),
RSTGEN(RGU_GPIO_DB2, CRU_SOFTRST_CON01, 6),
RSTGEN(RGU_GPIO_DB3, CRU_SOFTRST_CON01, 7),
RSTGEN(RGU_RXPHY, CRU_SOFTRST_CON02, 0),
RSTGEN(RGU_HDMIRX, CRU_SOFTRST_CON02, 2),
RSTGEN(RGU_TXPHY_CON, CRU_SOFTRST_CON02, 3),
RSTGEN(RGU_HDMITX, CRU_SOFTRST_CON02, 4),
RSTGEN(RGU_GVIHOST, CRU_SOFTRST_CON02, 5),
RSTGEN(RGU_DSI0, CRU_SOFTRST_CON02, 6),
RSTGEN(RGU_DSI1, CRU_SOFTRST_CON02, 7),
RSTGEN(RGU_CSI, CRU_SOFTRST_CON02, 8),
RSTGEN(RGU_TXDATA, CRU_SOFTRST_CON02, 9),
RSTGEN(RGU_DECODER, CRU_SOFTRST_CON02, 10),
RSTGEN(RGU_ENCODER, CRU_SOFTRST_CON02, 11),
RSTGEN(RGU_HDMIRX_PON, CRU_SOFTRST_CON02, 12),
RSTGEN(RGU_TXBYTEHS, CRU_SOFTRST_CON02, 13),
RSTGEN(RGU_TXESC, CRU_SOFTRST_CON02, 14),
};
static int rk628_rgu_update(struct rk628_cru *cru, unsigned long id, int assert)
{
const struct rk628_rgu_data *data = &rk628_rgu_data[id];
return regmap_write(cru->regmap, data->reg,
BIT(data->bit + 16) | (assert << data->bit));
}
static int rk628_rgu_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rk628_cru *cru = reset_to_cru(rcdev);
return rk628_rgu_update(cru, id, 1);
}
static int rk628_rgu_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rk628_cru *cru = reset_to_cru(rcdev);
return rk628_rgu_update(cru, id, 0);
}
static struct reset_control_ops rk628_rgu_ops = {
.assert = rk628_rgu_assert,
.deassert = rk628_rgu_deassert,
};
static int rk628_reset_controller_register(struct rk628_cru *cru)
{
struct device *dev = cru->dev;
cru->rcdev.owner = THIS_MODULE;
cru->rcdev.nr_resets = ARRAY_SIZE(rk628_rgu_data);
cru->rcdev.of_node = dev->of_node;
cru->rcdev.ops = &rk628_rgu_ops;
return devm_reset_controller_register(dev, &cru->rcdev);
}
static const struct regmap_range rk628_cru_readable_ranges[] = {
regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
};
static const struct regmap_access_table rk628_cru_readable_table = {
.yes_ranges = rk628_cru_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
};
static const struct regmap_config rk628_cru_regmap_config = {
.name = "cru",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = CRU_MAX_REGISTER,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.rd_table = &rk628_cru_readable_table,
};
static void rk628_cru_init(struct rk628_cru *cru)
{
u32 val = 0;
u8 mcu_mode;
regmap_read(cru->parent->grf, GRF_SYSTEM_STATUS0, &val);
mcu_mode = (val & I2C_ONLY_FLAG) ? 0 : 1;
if (mcu_mode)
return;
/* clock switch and first set gpll almost 99MHz */
regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff701d);
usleep_range(1000, 1100);
/* set clk_gpll_mux from gpll */
regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0004);
usleep_range(1000, 1100);
/* set pclk_logic from clk_gpll_mux and set pclk div 4 */
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0080);
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0083);
/* set cpll almost 400MHz */
regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff3063);
usleep_range(1000, 1100);
/* set clk_cpll_mux from clk_cpll */
regmap_write(cru->regmap, CRU_MODE_CON, 0xffff0005);
/* set pclk use cpll, now div is 4 */
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff0003);
/* set pclk use cpll, now div is 12 */
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b);
/* gpll 983.04MHz */
regmap_write(cru->regmap, CRU_GPLL_CON0, 0xffff1028);
usleep_range(1000, 1100);
/* set pclk use gpll, nuw div is 0xb */
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff008b);
/* set cpll 1188MHz */
regmap_write(cru->regmap, CRU_CPLL_CON0, 0xffff1063);
usleep_range(1000, 1100);
/* set pclk use cpll, and set pclk 99MHz */
regmap_write(cru->regmap, CRU_CLKSEL_CON00, 0xff000b);
}
static int rk628_cru_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_cru *cru;
struct clk **clk_table;
unsigned int i;
int ret;
cru = devm_kzalloc(dev, sizeof(*cru), GFP_KERNEL);
if (!cru)
return -ENOMEM;
cru->dev = dev;
cru->parent = rk628;
platform_set_drvdata(pdev, cru);
cru->regmap = devm_regmap_init_i2c(rk628->client,
&rk628_cru_regmap_config);
if (IS_ERR(cru->regmap)) {
ret = PTR_ERR(cru->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
rk628_cru_init(cru);
clk_table = devm_kcalloc(dev, CGU_NR_CLKS, sizeof(struct clk *),
GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
for (i = 0; i < CGU_NR_CLKS; i++)
clk_table[i] = ERR_PTR(-ENOENT);
cru->clk_data.clks = clk_table;
cru->clk_data.clk_num = CGU_NR_CLKS;
rk628_clk_register_plls(cru);
rk628_clk_register_muxes(cru);
rk628_clk_register_gates(cru);
rk628_clk_register_composites(cru);
rk628_reset_controller_register(cru);
clk_prepare_enable(clk_table[CGU_PCLK_LOGIC]);
return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
&cru->clk_data);
}
static int rk628_cru_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
return 0;
}
static const struct of_device_id rk628_cru_of_match[] = {
{ .compatible = "rockchip,rk628-cru", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_cru_of_match);
static struct platform_driver rk628_cru_driver = {
.driver = {
.name = "rk628-cru",
.of_match_table = of_match_ptr(rk628_cru_of_match),
},
.probe = rk628_cru_probe,
.remove = rk628_cru_remove,
};
module_platform_driver(rk628_cru_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 CRU driver");
MODULE_LICENSE("GPL v2");

1
drivers/gpu/drm/rockchip/Kconfig
View File

@@ -165,7 +165,6 @@ config ROCKCHIP_DW_HDCP2
Designware HDCP2 Controller.
source "drivers/gpu/drm/rockchip/rk618/Kconfig"
source "drivers/gpu/drm/rockchip/rk628/Kconfig"
source "drivers/gpu/drm/rockchip/ebc-dev/Kconfig"
endif

1
drivers/gpu/drm/rockchip/Makefile
View File

@@ -31,5 +31,4 @@ rockchipdrm-$(CONFIG_DRM_ROCKCHIP_VVOP) += rockchip_drm_vvop.o
obj-$(CONFIG_ROCKCHIP_DW_HDCP2) += dw_hdcp2.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o
obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618/
obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628/
obj-$(CONFIG_ROCKCHIP_EBC_DEV) += ebc-dev/

28
drivers/gpu/drm/rockchip/dw-dp.c
View File

@@ -933,6 +933,8 @@ static const struct drm_prop_enum_list color_format_enum_list[] = {
{ RK_IF_FORMAT_YCBCR444, "ycbcr444" },
{ RK_IF_FORMAT_YCBCR422, "ycbcr422" },
{ RK_IF_FORMAT_YCBCR420, "ycbcr420" },
{ RK_IF_FORMAT_YCBCR_HQ, "ycbcr_high_subsampling" },
{ RK_IF_FORMAT_YCBCR_LQ, "ycbcr_low_subsampling" },
};
static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format)
@@ -1360,7 +1362,7 @@ static int dw_dp_connector_atomic_check(struct drm_connector *conn,
}
if ((dp_new_state->color_format < RK_IF_FORMAT_RGB) ||
(dp_new_state->color_format > RK_IF_FORMAT_YCBCR420)) {
(dp_new_state->color_format > RK_IF_FORMAT_YCBCR_LQ)) {
dev_err(dp->dev, "set invalid color format:%d\n", dp_new_state->color_format);
return -EINVAL;
}
@@ -3250,6 +3252,21 @@ static struct edid *dw_dp_bridge_get_edid(struct drm_bridge *bridge,
return edid;
}
static void dw_dp_swap_fmts(u32 *fmt, int count)
{
int i;
u32 temp_fmt;
if (!count)
return;
for (i = 0; i < count / 2; i++) {
temp_fmt = fmt[i];
fmt[i] = fmt[count - i - 1];
fmt[count - i - 1] = temp_fmt;
}
}
static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
@@ -3314,7 +3331,11 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
continue;
if (dp_state->bpc != 0) {
if ((fmt->bpc != dp_state->bpc) ||
if (fmt->bpc != dp_state->bpc)
continue;
if (dp_state->color_format != RK_IF_FORMAT_YCBCR_HQ &&
dp_state->color_format != RK_IF_FORMAT_YCBCR_LQ &&
(fmt->color_format != BIT(dp_state->color_format)))
continue;
}
@@ -3325,6 +3346,9 @@ static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
output_fmts[j++] = fmt->bus_format;
}
if (dp_state->color_format == RK_IF_FORMAT_YCBCR_LQ)
dw_dp_swap_fmts(output_fmts, j);
*num_output_fmts = j;
return output_fmts;

8
drivers/gpu/drm/rockchip/rk628/Kconfig
View File

@@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config DRM_ROCKCHIP_RK628
tristate "Rockchip RK628 display bridge driver"
depends on DRM_ROCKCHIP
depends on MFD_RK628
help
Rockchip RK628 display bridge chips driver.

14
drivers/gpu/drm/rockchip/rk628/Makefile
View File

@@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Rockchip RK628 display bridge driver.
#
obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combrxphy.o \
rk628_combtxphy.o \
rk628_dsi.o \
rk628_gvi.o \
rk628_lvds.o \
rk628_post_process.o \
rk628_rgb.o \
rk628_hdmi.o \
rk628_hdmirx.o

1030
drivers/gpu/drm/rockchip/rk628/rk628_combrxphy.c
View File

File diff suppressed because it is too large Load Diff

520
drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
View File

@@ -1,520 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <asm/bitsperlong.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/mfd/rk628.h>
#include "rk628_combtxphy.h"
#define REG(x) ((x) + 0x90000)
#define COMBTXPHY_CON0 REG(0x0000)
#define SW_TX_IDLE_MASK GENMASK(29, 20)
#define SW_TX_IDLE(x) UPDATE(x, 29, 20)
#define SW_TX_PD_MASK GENMASK(17, 8)
#define SW_TX_PD(x) UPDATE(x, 17, 8)
#define SW_BUS_WIDTH_MASK GENMASK(6, 5)
#define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
#define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
#define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
#define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
#define SW_PD_PLL_MASK BIT(4)
#define SW_PD_PLL BIT(4)
#define SW_GVI_LVDS_EN_MASK BIT(3)
#define SW_GVI_LVDS_EN BIT(3)
#define SW_MIPI_DSI_EN_MASK BIT(2)
#define SW_MIPI_DSI_EN BIT(2)
#define SW_MODULEB_EN_MASK BIT(1)
#define SW_MODULEB_EN BIT(1)
#define SW_MODULEA_EN_MASK BIT(0)
#define SW_MODULEA_EN BIT(0)
#define COMBTXPHY_CON1 REG(0x0004)
#define COMBTXPHY_CON2 REG(0x0008)
#define COMBTXPHY_CON3 REG(0x000c)
#define COMBTXPHY_CON4 REG(0x0010)
#define COMBTXPHY_CON5 REG(0x0014)
#define SW_RATE(x) UPDATE(x, 26, 24)
#define SW_REF_DIV(x) UPDATE(x, 20, 16)
#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
#define COMBTXPHY_CON6 REG(0x0018)
#define COMBTXPHY_CON7 REG(0x001c)
#define SW_TX_RTERM_MASK GENMASK(22, 20)
#define SW_TX_RTERM(x) UPDATE(x, 22, 20)
#define SW_TX_MODE_MASK GENMASK(17, 16)
#define SW_TX_MODE(x) UPDATE(x, 17, 16)
#define SW_TX_CTL_CON5_MASK BIT(10)
#define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10)
#define SW_TX_CTL_CON4_MASK GENMASK(9, 8)
#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8)
#define BYPASS_095V_LDO_MASK BIT(3)
#define BYPASS_095V_LDO(x) UPDATE(x, 3, 3)
#define TX_COM_VOLT_ADJ_MASK GENMASK(2, 0)
#define TX_COM_VOLT_ADJ(x) UPDATE(x, 2, 0)
#define COMBTXPHY_CON8 REG(0x0020)
#define COMBTXPHY_CON9 REG(0x0024)
#define SW_DSI_FSET_EN_MASK BIT(29)
#define SW_DSI_FSET_EN BIT(29)
#define SW_DSI_RCAL_EN_MASK BIT(28)
#define SW_DSI_RCAL_EN BIT(28)
#define COMBTXPHY_CON10 REG(0x0028)
#define TX9_CKDRV_EN BIT(9)
#define TX8_CKDRV_EN BIT(8)
#define TX7_CKDRV_EN BIT(7)
#define TX6_CKDRV_EN BIT(6)
#define TX5_CKDRV_EN BIT(5)
#define TX4_CKDRV_EN BIT(4)
#define TX3_CKDRV_EN BIT(3)
#define TX2_CKDRV_EN BIT(2)
#define TX1_CKDRV_EN BIT(1)
#define TX0_CKDRV_EN BIT(0)
#define COMBTXPHY_MAX_REGISTER COMBTXPHY_CON10
struct rk628_combtxphy {
struct device *dev;
struct rk628 *parent;
struct regmap *grf;
struct regmap *regmap;
struct clk *pclk;
struct clk *ref_clk;
struct reset_control *rstc;
unsigned int flags;
u16 frac_div;
u8 ref_div;
u8 fb_div;
u8 rate_div;
u8 division_mode;
};
static int rk628_combtxphy_dsi_power_on(struct rk628_combtxphy *combtxphy)
{
u32 val;
int ret;
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK,
SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);
if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEA_EN_MASK, SW_MODULEA_EN);
if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEB_EN_MASK, SW_MODULEB_EN);
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(combtxphy->ref_div - 1) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL, 0);
ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
val, val & DPHY_PHYLOCK, 0, 1000);
if (ret < 0) {
dev_err(combtxphy->dev, "phy is not lock\n");
return ret;
}
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON9,
SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK,
SW_DSI_FSET_EN | SW_DSI_RCAL_EN);
usleep_range(200, 400);
return 0;
}
static int rk628_combtxphy_lvds_power_on(struct rk628_combtxphy *combtxphy)
{
u32 val;
int ret;
/* Adjust terminal resistance 133 ohm, bypass 0.95v ldo for driver. */
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON7,
SW_TX_RTERM_MASK | SW_TX_MODE_MASK |
BYPASS_095V_LDO_MASK | TX_COM_VOLT_ADJ_MASK,
SW_TX_RTERM(6) | SW_TX_MODE(3) |
BYPASS_095V_LDO(1) | TX_COM_VOLT_ADJ(0));
regmap_write(combtxphy->regmap, COMBTXPHY_CON10,
TX7_CKDRV_EN | TX2_CKDRV_EN);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK,
SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);
if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEA_EN_MASK, SW_MODULEA_EN);
if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEB_EN_MASK, SW_MODULEB_EN);
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(combtxphy->ref_div - 1) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL, 0);
ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
val, val & DPHY_PHYLOCK, 0, 1000);
if (ret < 0) {
dev_info(combtxphy->dev, "phy is not lock\n");
return ret;
}
usleep_range(100, 200);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK | SW_TX_PD_MASK, 0);
return 0;
}
static int rk628_combtxphy_gvi_power_on(struct rk628_combtxphy *combtxphy)
{
int ref_div = 0;
if (combtxphy->ref_div % 2) {
ref_div = combtxphy->ref_div - 1;
} else {
ref_div = BIT(4);
ref_div |= combtxphy->ref_div / 2 - 1;
}
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(ref_div) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK |
SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
SW_MODULEB_EN | SW_MODULEA_EN);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL | SW_TX_PD_MASK, 0);
usleep_range(100, 200);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK, 0);
return 0;
}
int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
combtxphy->division_mode = mode;
return 0;
}
EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode);
static int rk628_combtxphy_power_on(struct phy *phy)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
enum phy_mode mode = phy_get_mode(phy);
clk_prepare_enable(combtxphy->pclk);
reset_control_assert(combtxphy->rstc);
udelay(10);
reset_control_deassert(combtxphy->rstc);
udelay(10);
regcache_mark_dirty(combtxphy->regmap);
regcache_sync(combtxphy->regmap);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
switch (mode) {
case PHY_MODE_MIPI_DPHY:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(0));
return rk628_combtxphy_dsi_power_on(combtxphy);
case PHY_MODE_LVDS:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(1));
return rk628_combtxphy_lvds_power_on(combtxphy);
default:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(2));
return rk628_combtxphy_gvi_power_on(combtxphy);
}
return 0;
}
static int rk628_combtxphy_power_off(struct phy *phy)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK |
SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
clk_disable_unprepare(combtxphy->pclk);
return 0;
}
static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
int submode)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
unsigned int bus_width = phy_get_bus_width(phy);
unsigned int frac_rate, fin = 24;
unsigned long fvco, fpfd;
switch (mode) {
case PHY_MODE_MIPI_DPHY:
{
unsigned int fhsc = bus_width >> 8;
unsigned int flags = bus_width & 0xff;
fhsc = fin * (fhsc / fin);
if (fhsc < 80 || fhsc > 1500)
return -EINVAL;
else if (fhsc < 375)
combtxphy->rate_div = 4;
else if (fhsc < 750)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
combtxphy->flags = flags;
fvco = fhsc * 2 * combtxphy->rate_div;
combtxphy->ref_div = 1;
combtxphy->fb_div = fvco / 8 / fin;
frac_rate = fvco - (fin * 8 * combtxphy->fb_div);
if (frac_rate) {
frac_rate <<= 10;
frac_rate /= fin * 8;
combtxphy->frac_div = frac_rate;
} else {
combtxphy->frac_div = 0;
}
fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div);
fvco *= 8;
fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div);
fhsc = fvco / 2 / combtxphy->rate_div;
phy_set_bus_width(phy, fhsc);
break;
}
case PHY_MODE_LVDS:
{
unsigned int flags = bus_width & 0xff;
unsigned int rate = (bus_width >> 8) * 7;
combtxphy->flags = flags;
combtxphy->ref_div = 1;
combtxphy->fb_div = 14;
combtxphy->frac_div = 0;
if (rate < 500)
combtxphy->rate_div = 4;
else if (rate < 1000)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
break;
}
default:
{
unsigned int i, delta_freq, best_delta_freq, fb_div;
unsigned long ref_clk;
unsigned long long pre_clk;
if (bus_width < 500000 || bus_width > 4000000)
return -EINVAL;
else if (bus_width < 1000000)
combtxphy->rate_div = 4;
else if (bus_width < 2000000)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
fvco = bus_width * combtxphy->rate_div;
ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
if (combtxphy->division_mode)
ref_clk /= 2;
if (!ref_clk)
return -EINVAL;
/*
* the reference clock at PFD(FPFD = ref_clk / ref_div) about
* 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
* here to find the best rev_div.
*/
best_delta_freq = ref_clk;
for (i = 1; i <= 32; i++) {
fpfd = ref_clk / i;
delta_freq = abs(fpfd - 25000);
if (delta_freq < best_delta_freq) {
best_delta_freq = delta_freq;
combtxphy->ref_div = i;
}
}
/*
* ref_clk / ref_div * 8 * fb_div = FVCO
*/
pre_clk = (unsigned long long)fvco / 8 * combtxphy->ref_div * 1024;
do_div(pre_clk, ref_clk);
fb_div = pre_clk / 1024;
/*
* get the actually frequence
*/
bus_width = ref_clk / combtxphy->ref_div * 8;
bus_width *= fb_div;
bus_width /= combtxphy->rate_div;
combtxphy->frac_div = 0;
combtxphy->fb_div = fb_div;
phy_set_bus_width(phy, bus_width);
break;
}
}
return 0;
}
static const struct phy_ops rk628_combtxphy_ops = {
.set_mode = rk628_combtxphy_set_mode,
.power_on = rk628_combtxphy_power_on,
.power_off = rk628_combtxphy_power_off,
.owner = THIS_MODULE,
};
static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
regmap_reg_range(COMBTXPHY_CON0, COMBTXPHY_CON10),
};
static const struct regmap_access_table rk628_combtxphy_readable_table = {
.yes_ranges = rk628_combtxphy_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
};
static const struct regmap_config rk628_combtxphy_regmap_cfg = {
.name = "combtxphy",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.cache_type = REGCACHE_RBTREE,
.max_register = COMBTXPHY_MAX_REGISTER,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.rd_table = &rk628_combtxphy_readable_table,
};
static int rk628_combtxphy_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_combtxphy *combtxphy;
struct phy_provider *phy_provider;
struct phy *phy;
int ret;
combtxphy = devm_kzalloc(dev, sizeof(*combtxphy), GFP_KERNEL);
if (!combtxphy)
return -ENOMEM;
combtxphy->dev = dev;
combtxphy->parent = rk628;
combtxphy->grf = rk628->grf;
platform_set_drvdata(pdev, combtxphy);
combtxphy->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(combtxphy->pclk))
return PTR_ERR(combtxphy->pclk);
combtxphy->ref_clk = devm_clk_get(dev, "ref_clk");
if (IS_ERR(combtxphy->ref_clk)) {
dev_err(dev, "fail to get ref clk\n");
return PTR_ERR(combtxphy->ref_clk);
}
combtxphy->rstc = of_reset_control_get(dev->of_node, NULL);
if (IS_ERR(combtxphy->rstc)) {
ret = PTR_ERR(combtxphy->rstc);
dev_err(dev, "failed to get reset control: %d\n", ret);
return ret;
}
combtxphy->regmap = devm_regmap_init_i2c(rk628->client,
&rk628_combtxphy_regmap_cfg);
if (IS_ERR(combtxphy->regmap)) {
ret = PTR_ERR(combtxphy->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
phy = devm_phy_create(dev, NULL, &rk628_combtxphy_ops);
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
dev_err(dev, "failed to create phy: %d\n", ret);
return ret;
}
phy_set_drvdata(phy, combtxphy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(phy_provider)) {
ret = PTR_ERR(phy_provider);
dev_err(dev, "failed to register phy provider: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id rk628_combtxphy_of_match[] = {
{ .compatible = "rockchip,rk628-combtxphy", },
{}
};
MODULE_DEVICE_TABLE(of, rk628_combtxphy_of_match);
static struct platform_driver rk628_combtxphy_driver = {
.driver = {
.name = "rk628-combtxphy",
.of_match_table = of_match_ptr(rk628_combtxphy_of_match),
},
.probe = rk628_combtxphy_probe,
};
module_platform_driver(rk628_combtxphy_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 GVI/LVDS/MIPI Combo TX PHY driver");
MODULE_LICENSE("GPL v2");

13
drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.h
View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*/
#ifndef RK628_COMBTXPHY_H_
#define RK628_COMBTXPHY_H_
#include <linux/phy/phy.h>
int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode);
#endif

1395
drivers/gpu/drm/rockchip/rk628/rk628_dsi.c
View File

File diff suppressed because it is too large Load Diff

666
drivers/gpu/drm/rockchip/rk628/rk628_gvi.c
View File

@@ -1,666 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Sandy Huang <hjc@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/media-bus-format.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/rk628.h>
#include <drm/drm_of.h>
#include <drm/drm_atomic.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
#include "rk628_combtxphy.h"
#define HOSTREG(x) ((x) + 0x80000)
#define GVI_SYS_CTRL0 HOSTREG(0x0000)
#define GVI_SYS_CTRL1 HOSTREG(0x0004)
#define GVI_SYS_CTRL2 HOSTREG(0x0008)
#define GVI_SYS_CTRL3 HOSTREG(0x000c)
#define GVI_VERSION HOSTREG(0x0010)
#define GVI_SYS_RST HOSTREG(0x0014)
#define GVI_LINE_FLAG HOSTREG(0x0018)
#define GVI_STATUS HOSTREG(0x001c)
#define GVI_PLL_LOCK_TIMEOUT HOSTREG(0x0030)
#define GVI_HTPDN_TIMEOUT HOSTREG(0x0034)
#define GVI_LOCKN_TIMEOUT HOSTREG(0x0038)
#define GVI_WAIT_LOCKN HOSTREG(0x003C)
#define GVI_WAIT_HTPDN HOSTREG(0x0040)
#define GVI_INTR_EN HOSTREG(0x0050)
#define GVI_INTR_CLR HOSTREG(0x0054)
#define GVI_INTR_RAW_STATUS HOSTREG(0x0058)
#define GVI_INTR_STATUS HOSTREG(0x005c)
#define GVI_COLOR_BAR_CTRL HOSTREG(0x0060)
#define GVI_COLOR_BAR_HTIMING0 HOSTREG(0x0070)
#define GVI_COLOR_BAR_HTIMING1 HOSTREG(0x0074)
#define GVI_COLOR_BAR_VTIMING0 HOSTREG(0x0078)
#define GVI_COLOR_BAR_VTIMING1 HOSTREG(0x007c)
/* SYS_CTRL0 */
#define SYS_CTRL0_GVI_EN BIT(0)
#define SYS_CTRL0_AUTO_GATING BIT(1)
#define SYS_CTRL0_FRM_RST_EN BIT(2)
#define SYS_CTRL0_FRM_RST_MODE BIT(3)
#define SYS_CTRL0_LANE_NUM_MASK GENMASK(7, 4)
#define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
#define SYS_CTRL0_BYTE_MODE_MASK GENMASK(9, 8)
#define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
#define SYS_CTRL0_SECTION_NUM_MASK GENMASK(11, 10)
#define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
#define SYS_CTRL0_CDR_ENDIAN_SWAP BIT(12)
#define SYS_CTRL0_PACK_BYTE_SWAP BIT(13)
#define SYS_CTRL0_PACK_ENDIAN_SWAP BIT(14)
#define SYS_CTRL0_ENC8B10B_ENDIAN_SWAP BIT(15)
#define SYS_CTRL0_CDR_EN BIT(16)
#define SYS_CTRL0_ALN_EN BIT(17)
#define SYS_CTRL0_NOR_EN BIT(18)
#define SYS_CTRL0_ALN_NOR_MODE BIT(19)
#define SYS_CTRL0_GVI_MASK GENMASK(19, 16)
#define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
#define SYS_CTRL0_SCRAMBLER_EN BIT(20)
#define SYS_CTRL0_ENCODE8B10B_EN BIT(21)
#define SYS_CTRL0_INIT_RD_EN BIT(22)
#define SYS_CTRL0_INIT_RD_VALUE BIT(23)
#define SYS_CTRL0_FORCE_HTPDN_EN BIT(24)
#define SYS_CTRL0_FORCE_HTPDN_VALUE BIT(25)
#define SYS_CTRL0_FORCE_PLL_EN BIT(26)
#define SYS_CTRL0_FORCE_PLL_VALUE BIT(27)
#define SYS_CTRL0_FORCE_LOCKN_EN BIT(28)
#define SYS_CTRL0_FORCE_LOCKN_VALUE BIT(29)
/* SYS_CTRL1 */
#define SYS_CTRL1_COLOR_DEPTH_MASK GENMASK(3, 0)
#define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
#define SYS_CTRL1_DUAL_PIXEL_EN BIT(4)
#define SYS_CTRL1_TIMING_ALIGN_EN BIT(8)
#define SYS_CTRL1_LANE_ALIGN_EN BIT(9)
#define SYS_CTRL1_DUAL_PIXEL_SWAP BIT(12)
#define SYS_CTRL1_RB_SWAP BIT(13)
#define SYS_CTRL1_YC_SWAP BIT(14)
#define SYS_CTRL1_WHOLE_FRM_EN BIT(16)
#define SYS_CTRL1_NOR_PROTECT BIT(17)
#define SYS_CTRL1_RD_WCNT_UPDATE BIT(31)
/* SYS_CTRL2 */
#define SYS_CTRL2_AFIFO_READ_THOLD_MASK GENMASK(7, 0)
#define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD_MASK GENMASK(23, 16)
#define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD_MASK GENMASK(31, 24)
#define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
/* SYS_CTRL3 */
#define SYS_CTRL3_LANE0_SEL_MASK GENMASK(2, 0)
#define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
#define SYS_CTRL3_LANE1_SEL_MASK GENMASK(6, 4)
#define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
#define SYS_CTRL3_LANE2_SEL_MASK GENMASK(10, 8)
#define SYS_CTRL3_LANE2_SEL(x) UPDATE(x, 10, 8)
#define SYS_CTRL3_LANE3_SEL_MASK GENMASK(14, 12)
#define SYS_CTRL3_LANE3_SEL(x) UPDATE(x, 14, 12)
#define SYS_CTRL3_LANE4_SEL_MASK GENMASK(18, 16)
#define SYS_CTRL3_LANE4_SEL(x) UPDATE(x, 18, 16)
#define SYS_CTRL3_LANE5_SEL_MASK GENMASK(22, 20)
#define SYS_CTRL3_LANE5_SEL(x) UPDATE(x, 22, 20)
#define SYS_CTRL3_LANE6_SEL_MASK GENMASK(26, 24)
#define SYS_CTRL3_LANE6_SEL(x) UPDATE(x, 26, 24)
#define SYS_CTRL3_LANE7_SEL_MASK GENMASK(30, 28)
#define SYS_CTRL3_LANE7_SEL(x) UPDATE(x, 30, 28)
/* VERSIION */
#define VERSION_VERSION(x) UPDATE(x, 31, 0)
/* SYS_RESET*/
#define SYS_RST_SOFT_RST BIT(0)
/* LINE_FLAG */
#define LINE_FLAG_LANE_FLAG0_MASK GENMASK(15, 0)
#define LINE_FLAG_LANE_FLAG0(x) UPDATE(x, 15, 0)
#define LINE_FLAG_LANE_FLAG1_MASK GENMASK(31, 16)
#define LINE_FLAG_LANE_FLAG1(x) UPDATE(x, 31, 16)
/* STATUS */
#define STATUS_HTDPN BIT(4)
#define STATUS_LOCKN BIT(5)
#define STATUS_PLL_LOCKN BIT(6)
#define STATUS_AFIFO0_WCNT_MASK GENMASK(23, 16)
#define STATUS_AFIFO0_WCNT(x) UPDATE(x, 23, 16)
#define STATUS_AFIFO1_WCNT_MASK GENMASK(31, 24)
#define STATUS_AFIFO1_WCNT(x) UPDATE(x, 31, 24)
/* PLL_LTIMEOUT */
#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT_MASK GENMASK(31, 0)
#define PLL_LOCK_TIMEOUT_PLL_LOCK_TIME_OUT(x) UPDATE(x, 31, 0)
/* HTPDNEOUT */
#define HTPDN_TIMEOUT_HTPDN_TIME_OUT_MASK GENMASK(31, 0)
#define HTPDN_TIMEOUT_HTPDN_TIME_OUT(x) UPDATE(x, 31, 0)
/* LOCKNEOUT */
#define LOCKN_TIMEOUT_LOCKN_TIME_OUT_MASK GENMASK(31, 0)
#define LOCKN_TIMEOUT_LOCKN_TIME_OUT(x) UPDATE(x, 31, 0)
/* WAIT_LOCKN */
#define WAIT_LOCKN_WAIT_LOCKN_TIME_MASK GENMASK(30, 0)
#define WAIT_LOCKN_WAIT_LOCKN_TIME(x) UPDATE(x, 30, 0)
#define WAIT_LOCKN_WAIT_LOCKN_TIME_EN BIT(31)
/* WAIT_HTPDN */
#define WAIT_HTPDN_WAIT_HTPDN_TIME_MASK GENMASK(30, 0)
#define WAIT_HTPDN_WAIT_HTPDN_TIME(x) UPDATE(x, 30, 0)
#define WAIT_HTPDN_WAIT_HTPDN_EN BIT(31)
/* INTR_EN */
#define INTR_EN_INTR_FRM_ST_EN BIT(0)
#define INTR_EN_INTR_PLL_LOCK_EN BIT(1)
#define INTR_EN_INTR_HTPDN_EN BIT(2)
#define INTR_EN_INTR_LOCKN_EN BIT(3)
#define INTR_EN_INTR_PLL_TIMEOUT_EN BIT(4)
#define INTR_EN_INTR_HTPDN_TIMEOUT_EN BIT(5)
#define INTR_EN_INTR_LOCKN_TIMEOUT_EN BIT(6)
#define INTR_EN_INTR_LINE_FLAG0_EN BIT(8)
#define INTR_EN_INTR_LINE_FLAG1_EN BIT(9)
#define INTR_EN_INTR_AFIFO_OVERFLOW_EN BIT(10)
#define INTR_EN_INTR_AFIFO_UNDERFLOW_EN BIT(11)
#define INTR_EN_INTR_PLL_ERR_EN BIT(12)
#define INTR_EN_INTR_HTPDN_ERR_EN BIT(13)
#define INTR_EN_INTR_LOCKN_ERR_EN BIT(14)
/* INTR_CLR*/
#define INTR_CLR_INTR_FRM_ST_CLR BIT(0)
#define INTR_CLR_INTR_PLL_LOCK_CLR BIT(1)
#define INTR_CLR_INTR_HTPDN_CLR BIT(2)
#define INTR_CLR_INTR_LOCKN_CLR BIT(3)
#define INTR_CLR_INTR_PLL_TIMEOUT_CLR BIT(4)
#define INTR_CLR_INTR_HTPDN_TIMEOUT_CLR BIT(5)
#define INTR_CLR_INTR_LOCKN_TIMEOUT_CLR BIT(6)
#define INTR_CLR_INTR_LINE_FLAG0_CLR BIT(8)
#define INTR_CLR_INTR_LINE_FLAG1_CLR BIT(9)
#define INTR_CLR_INTR_AFIFO_OVERFLOW_CLR BIT(10)
#define INTR_CLR_INTR_AFIFO_UNDERFLOW_CLR BIT(11)
#define INTR_CLR_INTR_PLL_ERR_CLR BIT(12)
#define INTR_CLR_INTR_HTPDN_ERR_CLR BIT(13)
#define INTR_CLR_INTR_LOCKN_ERR_CLR BIT(14)
/* INTR_RAW_STATUS */
#define INTR_RAW_STATUS_RAW_INTR_FRM_ST BIT(0)
#define INTR_RAW_STATUS_RAW_INTR_PLL_LOCK BIT(1)
#define INTR_RAW_STATUS_RAW_INTR_HTPDN BIT(2)
#define INTR_RAW_STATUS_RAW_INTR_LOCKN BIT(3)
#define INTR_RAW_STATUS_RAW_INTR_PLL_TIMEOUT BIT(4)
#define INTR_RAW_STATUS_RAW_INTR_HTPDN_TIMEOUT BIT(5)
#define INTR_RAW_STATUS_RAW_INTR_LOCKN_TIMEOUT BIT(6)
#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG0 BIT(8)
#define INTR_RAW_STATUS_RAW_INTR_LINE_FLAG1 BIT(9)
#define INTR_RAW_STATUS_RAW_INTR_AFIFO_OVERFLOW BIT(10)
#define INTR_RAW_STATUS_RAW_INTR_AFIFO_UNDERFLOW BIT(11)
#define INTR_RAW_STATUS_RAW_INTR_PLL_ERR BIT(12)
#define INTR_RAW_STATUS_RAW_INTR_HTPDN_ERR BIT(13)
#define INTR_RAW_STATUS_RAW_INTR_LOCKN_ERR BIT(14)
/* INTR_STATUS */
#define INTR_STATUS_INTR_FRM_ST BIT(0)
#define INTR_STATUS_INTR_PLL_LOCK BIT(1)
#define INTR_STATUS_INTR_HTPDN BIT(2)
#define INTR_STATUS_INTR_LOCKN BIT(3)
#define INTR_STATUS_INTR_PLL_TIMEOUT BIT(4)
#define INTR_STATUS_INTR_HTPDN_TIMEOUT BIT(5)
#define INTR_STATUS_INTR_LOCKN_TIMEOUT BIT(6)
#define INTR_STATUS_INTR_LINE_FLAG0 BIT(8)
#define INTR_STATUS_INTR_LINE_FLAG1 BIT(9)
#define INTR_STATUS_INTR_AFIFO_OVERFLOW BIT(10)
#define INTR_STATUS_INTR_AFIFO_UNDERFLOW BIT(11)
#define INTR_STATUS_INTR_PLL_ERR BIT(12)
#define INTR_STATUS_INTR_HTPDN_ERR BIT(13)
#define INTR_STATUS_INTR_LOCKN_ERR BIT(14)
/* COLOR_BAR_CTRL */
#define COLOR_BAR_EN BIT(0)
#define COLOR_DEPTH_RGB_YUV444_18BIT 0
#define COLOR_DEPTH_RGB_YUV444_24BIT 1
#define COLOR_DEPTH_RGB_YUV444_30BIT 2
#define COLOR_DEPTH_YUV422_16BIT 8
#define COLOR_DEPTH_YUV422_20BIT 9
enum gvi_byte_mode {
GVI_3BYTE_MODE = 0,
GVI_4BYTE_MODE,
GVI_5BYTE_MODE,
};
struct rk628_gvi {
struct drm_bridge base;
struct drm_connector connector;
struct drm_panel *panel;
struct drm_display_mode mode;
struct device *dev;
struct regmap *grf;
struct regmap *regmap;
struct clk *pclk;
struct reset_control *rst;
struct phy *phy;
struct rk628 *parent;
u32 lane_mbps;
u32 bus_format;
u32 lane_num;
u8 color_depth;
u8 byte_mode;
bool division_mode;
};
static inline struct rk628_gvi *bridge_to_gvi(struct drm_bridge *b)
{
return container_of(b, struct rk628_gvi, base);
}
static inline struct rk628_gvi *connector_to_gvi(struct drm_connector *c)
{
return container_of(c, struct rk628_gvi, connector);
}
static struct drm_encoder *rk628_gvi_connector_best_encoder(struct drm_connector
*connector)
{
struct rk628_gvi *gvi = connector_to_gvi(connector);
return gvi->base.encoder;
}
static int rk628_gvi_connector_get_modes(struct drm_connector *connector)
{
struct rk628_gvi *gvi = connector_to_gvi(connector);
struct drm_display_info *info = &connector->display_info;
int num_modes;
num_modes = drm_panel_get_modes(gvi->panel, connector);
if (info->num_bus_formats)
gvi->bus_format = info->bus_formats[0];
else
gvi->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
switch (gvi->bus_format) {
case MEDIA_BUS_FMT_RGB666_1X18:
gvi->byte_mode = 3;
gvi->color_depth = COLOR_DEPTH_RGB_YUV444_18BIT;
break;
case MEDIA_BUS_FMT_RGB888_1X24:
gvi->byte_mode = 4;
gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
break;
case MEDIA_BUS_FMT_RGB101010_1X30:
gvi->byte_mode = 4;
gvi->color_depth = COLOR_DEPTH_RGB_YUV444_30BIT;
break;
case MEDIA_BUS_FMT_YUYV8_1X16:
gvi->byte_mode = 3;
gvi->color_depth = COLOR_DEPTH_YUV422_16BIT;
break;
case MEDIA_BUS_FMT_YUYV10_1X20:
gvi->byte_mode = 3;
gvi->color_depth = COLOR_DEPTH_YUV422_20BIT;
break;
default:
gvi->byte_mode = 3;
gvi->color_depth = COLOR_DEPTH_RGB_YUV444_24BIT;
dev_info(gvi->dev, "unsupported bus_format: 0x%x\n",
gvi->bus_format);
break;
}
info->edid_hdmi_rgb444_dc_modes = 0;
info->edid_hdmi_ycbcr444_dc_modes = 0;
info->hdmi.y420_dc_modes = 0;
info->color_formats = 0;
info->max_tmds_clock = 300000;
connector->ycbcr_420_allowed = true;
num_modes += rk628_scaler_add_src_mode(gvi->parent, connector);
return num_modes;
}
static const
struct drm_connector_helper_funcs rk628_gvi_connector_helper_funcs = {
.get_modes = rk628_gvi_connector_get_modes,
.best_encoder = rk628_gvi_connector_best_encoder,
};
static enum drm_connector_status
rk628_gvi_connector_detect(struct drm_connector *connector, bool force)
{
return connector_status_connected;
}
static void rk628_gvi_connector_destroy(struct drm_connector *connector)
{
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs rk628_gvi_connector_funcs = {
.detect = rk628_gvi_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = rk628_gvi_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static unsigned int rk628_gvi_get_lane_rate(struct rk628_gvi *gvi)
{
struct device *dev = gvi->dev;
const struct drm_display_mode *mode = &gvi->mode;
u32 lane_bit_rate, min_lane_rate = 500000, max_lane_rate = 4000000;
u64 total_bw;
/* optional override of the desired bandwidth */
if (!of_property_read_u32
(dev->of_node, "rockchip,lane-rate", &lane_bit_rate))
return lane_bit_rate;
/**
* [ENCODER TOTAL BIT-RATE](bps) = [byte mode](byte) x 10 / [pixel clock](HZ)
*
* lane_bit_rate = [total bit-rate](bps) / [lane number]
*
* 500Mbps <= lane_bit_rate <= 4Gbps
*/
total_bw = (unsigned long long)gvi->byte_mode * 10 * mode->clock; /* Kbps */
do_div(total_bw, gvi->lane_num);
lane_bit_rate = total_bw;
if (lane_bit_rate < min_lane_rate)
lane_bit_rate = min_lane_rate;
if (lane_bit_rate > max_lane_rate)
lane_bit_rate = max_lane_rate;
return lane_bit_rate;
}
static void rk628_gvi_enable_color_bar(struct rk628_gvi *gvi)
{
const struct drm_display_mode *mode = &gvi->mode;
struct videomode vm;
u16 hsync_len, hact_st, hact_end, htotal;
u16 vsync_len, vact_st, vact_end, vtotal;
drm_display_mode_to_videomode(mode, &vm);
if (gvi->division_mode) {
hsync_len = vm.hsync_len / 2;
hact_st = (vm.hsync_len + vm.hback_porch) / 2;
hact_end = (vm.hsync_len + vm.hback_porch + vm.hactive) / 2;
htotal = mode->htotal / 2;
} else {
hsync_len = vm.hsync_len;
hact_st = vm.hsync_len + vm.hback_porch;
hact_end = vm.hsync_len + vm.hback_porch + vm.hactive;
htotal = mode->htotal;
}
vsync_len = vm.vsync_len;
vact_st = vsync_len + vm.vback_porch;
vact_end = vact_st + vm.vactive;
vtotal = mode->vtotal;
regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING0,
hact_st << 16 | hsync_len);
regmap_write(gvi->regmap, GVI_COLOR_BAR_HTIMING1,
(htotal - 1) << 16 | hact_end);
regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING0,
vact_st << 16 | vsync_len);
regmap_write(gvi->regmap, GVI_COLOR_BAR_VTIMING1,
(vtotal - 1) << 16 | vact_end);
regmap_write_bits(gvi->regmap, GVI_COLOR_BAR_CTRL, COLOR_BAR_EN, 0);
}
static void rk628_gvi_pre_enable(struct rk628_gvi *gvi)
{
clk_prepare_enable(gvi->pclk);
/* gvi reset */
regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST,
SYS_RST_SOFT_RST);
udelay(10);
regmap_write_bits(gvi->regmap, GVI_SYS_RST, SYS_RST_SOFT_RST, 0);
udelay(10);
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_LANE_NUM_MASK,
SYS_CTRL0_LANE_NUM(gvi->lane_num - 1));
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_BYTE_MODE_MASK,
SYS_CTRL0_BYTE_MODE(gvi->byte_mode ==
3 ? 0 : (gvi->byte_mode ==
4 ? 1 : 2)));
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0,
SYS_CTRL0_SECTION_NUM_MASK,
SYS_CTRL0_SECTION_NUM(gvi->division_mode));
regmap_update_bits(gvi->grf, GRF_POST_PROC_CON, SW_SPLIT_EN,
gvi->division_mode ? SW_SPLIT_EN : 0);
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_DUAL_PIXEL_EN,
gvi->division_mode ? SYS_CTRL1_DUAL_PIXEL_EN : 0);
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_FRM_RST_EN, 0);
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL1, SYS_CTRL1_LANE_ALIGN_EN, 0);
}
static void rk628_gvi_post_enable(struct rk628_gvi *gvi)
{
u32 val;
val = SYS_CTRL0_GVI_EN | SYS_CTRL0_AUTO_GATING;
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, val, 3);
}
static void rk628_gvi_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_gvi *gvi = bridge_to_gvi(bridge);
unsigned int rate = rk628_gvi_get_lane_rate(gvi);
int ret;
regmap_update_bits(gvi->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_GVI));
phy_set_bus_width(gvi->phy, rate);
rk628_combtxphy_set_gvi_division_mode(gvi->phy, gvi->division_mode);
ret = phy_set_mode(gvi->phy, 0);
if (ret) {
dev_err(gvi->dev, "failed to set phy mode: %d\n", ret);
return;
}
phy_power_on(gvi->phy);
gvi->lane_mbps = phy_get_bus_width(gvi->phy);
rk628_gvi_pre_enable(gvi);
drm_panel_prepare(gvi->panel);
rk628_gvi_enable_color_bar(gvi);
rk628_gvi_post_enable(gvi);
drm_panel_enable(gvi->panel);
dev_info(gvi->dev,
"GVI-Link bandwidth: %d x %d Mbps, Byte mode: %d, Color Depty: %d, %s division mode\n",
gvi->lane_mbps, gvi->lane_num, gvi->byte_mode,
gvi->color_depth, gvi->division_mode ? "two" : "one");
}
static void rk628_gvi_post_disable(struct drm_bridge *bridge)
{
struct rk628_gvi *gvi = bridge_to_gvi(bridge);
regmap_write_bits(gvi->regmap, GVI_SYS_CTRL0, SYS_CTRL0_GVI_EN, 0);
}
static void rk628_gvi_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_gvi *gvi = bridge_to_gvi(bridge);
drm_panel_disable(gvi->panel);
drm_panel_unprepare(gvi->panel);
rk628_gvi_post_disable(bridge);
clk_disable_unprepare(gvi->pclk);
phy_power_off(gvi->phy);
}
static int rk628_gvi_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct rk628_gvi *gvi = bridge_to_gvi(bridge);
struct drm_connector *connector = &gvi->connector;
struct drm_device *drm = bridge->dev;
int ret;
if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
return 0;
ret = drm_connector_init(drm, connector, &rk628_gvi_connector_funcs,
DRM_MODE_CONNECTOR_LVDS);
if (ret) {
dev_err(gvi->dev, "Failed to initialize connector with drm\n");
return ret;
}
drm_connector_helper_add(connector, &rk628_gvi_connector_helper_funcs);
drm_connector_attach_encoder(connector, bridge->encoder);
return 0;
}
static void rk628_gvi_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct rk628_gvi *gvi = bridge_to_gvi(bridge);
rk628_mode_copy(gvi->parent, &gvi->mode, mode);
dev_info(gvi->dev, "src mode: %dx%d, clk: %d, dst mode: %dx%d, clk: %d\n",
mode->hdisplay, mode->vdisplay, mode->clock,
gvi->mode.hdisplay, gvi->mode.vdisplay, gvi->mode.clock);
}
static const struct drm_bridge_funcs rk628_gvi_bridge_funcs = {
.attach = rk628_gvi_bridge_attach,
.enable = rk628_gvi_bridge_enable,
.disable = rk628_gvi_bridge_disable,
.mode_set = rk628_gvi_bridge_mode_set,
};
static const struct regmap_range rk628_gvi_readable_ranges[] = {
regmap_reg_range(GVI_SYS_CTRL0, GVI_COLOR_BAR_VTIMING1),
};
static const struct regmap_access_table rk628_gvi_readable_table = {
.yes_ranges = rk628_gvi_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(rk628_gvi_readable_ranges),
};
static const struct regmap_config rk628_gvi_regmap_cfg = {
.name = "gvi",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = GVI_COLOR_BAR_VTIMING1,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.rd_table = &rk628_gvi_readable_table,
};
static int rk628_gvi_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_gvi *gvi;
int ret = 0;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
gvi = devm_kzalloc(dev, sizeof(*gvi), GFP_KERNEL);
if (!gvi)
return -ENOMEM;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
&gvi->panel, NULL);
if (ret)
return ret;
gvi->dev = dev;
gvi->parent = rk628;
gvi->division_mode = of_property_read_bool(dev->of_node,
"rockchip,division-mode");
ret = of_property_read_u32(dev->of_node, "rockchip,lane-num",
&gvi->lane_num);
if (ret) {
dev_err(gvi->dev, "Failed to get lane num\n");
gvi->lane_num = 4;
}
platform_set_drvdata(pdev, gvi);
gvi->grf = rk628->grf;
if (!gvi->grf)
return -ENODEV;
gvi->regmap = devm_regmap_init_i2c(rk628->client,
&rk628_gvi_regmap_cfg);
if (IS_ERR(gvi->regmap)) {
ret = PTR_ERR(gvi->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
gvi->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(gvi->pclk)) {
ret = PTR_ERR(gvi->pclk);
dev_err(dev, "failed to get pclk: %d\n", ret);
return ret;
}
gvi->rst = of_reset_control_get(dev->of_node, NULL);
if (IS_ERR(gvi->rst)) {
ret = PTR_ERR(gvi->rst);
dev_err(dev, "failed to get reset control: %d\n", ret);
return ret;
}
gvi->phy = devm_of_phy_get(dev, dev->of_node, NULL);
if (IS_ERR(gvi->phy)) {
ret = PTR_ERR(gvi->phy);
dev_err(dev, "failed to get phy: %d\n", ret);
return ret;
}
gvi->base.funcs = &rk628_gvi_bridge_funcs;
gvi->base.of_node = dev->of_node;
drm_bridge_add(&gvi->base);
return 0;
}
static int rk628_gvi_remove(struct platform_device *pdev)
{
struct rk628_gvi *gvi = platform_get_drvdata(pdev);
drm_bridge_remove(&gvi->base);
return 0;
}
static const struct of_device_id rk628_gvi_of_match[] = {
{.compatible = "rockchip,rk628-gvi",},
{},
};
MODULE_DEVICE_TABLE(of, rk628_gvi_of_match);
static struct platform_driver rk628_gvi_driver = {
.driver = {
.name = "rk628-gvi",
.of_match_table = of_match_ptr(rk628_gvi_of_match),
},
.probe = rk628_gvi_probe,
.remove = rk628_gvi_remove,
};
module_platform_driver(rk628_gvi_driver);
MODULE_AUTHOR("Sandy Huang <hjc@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 GVI driver");
MODULE_LICENSE("GPL v2");

1623
drivers/gpu/drm/rockchip/rk628/rk628_hdmi.c
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980
drivers/gpu/drm/rockchip/rk628/rk628_hdmirx.c
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@@ -1,980 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Algea Cao <algea.cao@rock-chips.com>
*/
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/timer.h>
#include <linux/workqueue.h>
#include <linux/mfd/rk628.h>
#include <linux/phy/phy.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_print.h>
#include <drm/display/drm_dp_helper.h>
#include <drm/drm_of.h>
#define REG(x) ((x) + 0x30000)
#define HDMI_RX_HDMI_SETUP_CTRL REG(0x0000)
#define HOT_PLUG_DETECT_MASK BIT(0)
#define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
#define HDMI_RX_HDMI_OVR_CTRL REG(0x0004)
#define HDMI_RX_HDMI_TIMER_CTRL REG(0x0008)
#define HDMI_RX_HDMI_RES_OVR REG(0x0010)
#define HDMI_RX_HDMI_RES_STS REG(0x0014)
#define HDMI_RX_HDMI_PLL_CTRL REG(0x0018)
#define HDMI_RX_HDMI_PLL_FRQSET1 REG(0x001c)
#define HDMI_RX_HDMI_PLL_FRQSET2 REG(0x0020)
#define HDMI_RX_HDMI_PLL_PAR1 REG(0x0024)
#define HDMI_RX_HDMI_PLL_PAR2 REG(0x0028)
#define HDMI_RX_HDMI_PLL_PAR3 REG(0x002c)
#define HDMI_RX_HDMI_PLL_LCK_STS REG(0x0030)
#define HDMI_RX_HDMI_CLK_CTRL REG(0x0034)
#define HDMI_RX_HDMI_PCB_CTRL REG(0x0038)
#define SEL_PIXCLKSRC_MASK GENMASK(19, 18)
#define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
#define HDMI_RX_HDMI_PHS_CTR REG(0x0040)
#define HDMI_RX_HDMI_PHS_USED REG(0x0044)
#define HDMI_RX_HDMI_MISC_CTRL REG(0x0048)
#define HDMI_RX_HDMI_EQOFF_CTRL REG(0x004c)
#define HDMI_RX_HDMI_EQGAIN_CTRL REG(0x0050)
#define HDMI_RX_HDMI_EQCAL_STS REG(0x0054)
#define HDMI_RX_HDMI_EQRESULT REG(0x0058)
#define HDMI_RX_HDMI_EQ_MEAS_CTRL REG(0x005c)
#define HDMI_RX_HDMI_WR_CFG REG(0x0060)
#define HDMI_RX_HDMI_CTRL REG(0x0064)
#define HDMI_RX_HDMI_MODE_RECOVER REG(0x0080)
#define PREAMBLE_CNT_LIMIT_MASK GENMASK(31, 27)
#define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
#define OESSCTL3_THR_MASK GENMASK(20, 19)
#define OESSCTL3_THR(x) UPDATE(x, 20, 19)
#define SPIKE_FILTER_EN_MASK BIT(18)
#define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
#define DVI_MODE_HYST_MASK GENMASK(17, 13)
#define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
#define HDMI_MODE_HYST_MASK GENMASK(12, 8)
#define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
#define HDMI_MODE_MASK GENMASK(7, 6)
#define HDMI_MODE(x) UPDATE(x, 7, 6)
#define GB_DET_MASK GENMASK(5, 4)
#define GB_DET(x) UPDATE(x, 5, 4)
#define EESS_OESS_MASK GENMASK(3, 2)
#define EESS_OESS(x) UPDATE(x, 3, 2)
#define SEL_CTL01_MASK GENMASK(1, 0)
#define SEL_CTL01(x) UPDATE(x, 1, 0)
#define HDMI_RX_HDMI_ERROR_PROTECT REG(0x0084)
#define RG_BLOCK_OFF_MASK BIT(20)
#define RG_BLOCK_OFF(x) UPDATE(x, 20, 20)
#define BLOCK_OFF_MASK BIT(19)
#define BLOCK_OFF(x) UPDATE(x, 19, 19)
#define VALID_MODE_MASK GENMASK(18, 16)
#define VALID_MODE(x) UPDATE(x, 18, 16)
#define CTRL_FILT_SEN_MASK GENMASK(13, 12)
#define CTRL_FILT_SEN(x) UPDATE(x, 13, 12)
#define VS_FILT_SENS_MASK GENMASK(11, 10)
#define VS_FILT_SENS(x) UPDATE(x, 11, 10)
#define HS_FILT_SENS_MASK GENMASK(9, 8)
#define HS_FILT_SENS(x) UPDATE(x, 9, 8)
#define DE_MEASURE_MODE_MASK GENMASK(7, 6)
#define DE_MEASURE_MODE(x) UPDATE(x, 7, 6)
#define DE_REGEN_MASK BIT(5)
#define DE_REGEN(x) UPDATE(x, 5, 5)
#define DE_FILTER_SENS_MASK GENMASK(4, 3)
#define DE_FILTER_SENS(x) UPDATE(x, 4, 3)
#define HDMI_RX_HDMI_ERD_STS REG(0x0088)
#define HDMI_RX_HDMI_SYNC_CTRL REG(0x0090)
#define VS_POL_ADJ_MODE_MASK GENMASK(4, 3)
#define VS_POL_ADJ_MODE(x) UPDATE(x, 4, 3)
#define HS_POL_ADJ_MODE_MASK GENMASK(2, 1)
#define HS_POL_ADJ_MODE(x) UPDATE(x, 2, 1)
#define HDMI_RX_HDMI_CKM_EVLTM REG(0x0094)
#define LOCK_HYST_MASK GENMASK(21, 20)
#define LOCK_HYST(x) UPDATE(x, 21, 20)
#define CLK_HYST_MASK GENMASK(18, 16)
#define CLK_HYST(x) UPDATE(x, 18, 16)
#define EVAL_TIME_MASK GENMASK(15, 4)
#define EVAL_TIME(x) UPDATE(x, 15, 4)
#define HDMI_RX_HDMI_CKM_F REG(0x0098)
#define HDMIRX_MAXFREQ_MASK GENMASK(31, 16)
#define HDMIRX_MAXFREQ(x) UPDATE(x, 31, 16)
#define MINFREQ_MASK GENMASK(15, 0)
#define MINFREQ(x) UPDATE(x, 15, 0)
#define HDMI_RX_HDMI_CKM_RESULT REG(0x009c)
#define HDMI_RX_HDMI_PVO_CONFIG REG(0x00a0)
#define HDMI_RX_HDMI_RESMPL_CTRL REG(0x00a4)
#define MAN_VID_DEREPEAT_MASK GENMASK(4, 1)
#define MAN_VID_DEREPEAT(x) UPDATE(x, 4, 1)
#define AUTO_DEREPEAT_MASK BIT(0)
#define AUTO_DEREPEAT(x) UPDATE(x, 0, 0)
#define HDMI_RX_HDMI_DCM_CTRL REG(0x00a8)
#define DCM_DEFAULT_PHASE_MASK BIT(18)
#define DCM_DEFAULT_PHASE(x) UPDATE(x, 18, 18)
#define DCM_COLOUR_DEPTH_SEL_MASK BIT(12)
#define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12)
#define DCM_COLOUR_DEPTH_MASK GENMASK(11, 8)
#define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8)
#define DCM_GCP_ZERO_FIELDS_MASK GENMASK(5, 2)
#define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2)
#define HDMI_RX_HDMI_VM_CFG_CH_0_1 REG(0x00b0)
#define HDMI_RX_HDMI_VM_CFG_CH2 REG(0x00b4)
#define HDMI_RX_HDMI_SPARE REG(0x00b8)
#define HDMI_RX_HDMI_STS REG(0x00bc)
#define HDMI_RX_HDCP_CTRL REG(0x00c0)
#define HDCP_ENABLE_MASK BIT(24)
#define HDCP_ENABLE(x) UPDATE(x, 24, 24)
#define FREEZE_HDCP_FSM_MASK BIT(21)
#define FREEZE_HDCP_FSM(x) UPDATE(x, 21, 21)
#define FREEZE_HDCP_STATE_MASK GENMASK(20, 15)
#define FREEZE_HDCP_STATE(x) UPDATE(x, 20, 15)
#define HDCP_CTL_MASK GENMASK(9, 8)
#define HDCP_CTL(x) UPDATE(x, 9, 8)
#define HDCP_RI_RATE_MASK GENMASK(7, 6)
#define HDCP_RI_RATE(x) UPDATE(x, 7, 6)
#define KEY_DECRYPT_ENABLE_MASK BIT(1)
#define KEY_DECRYPT_ENABLE(x) UPDATE(x, 1, 1)
#define HDCP_ENC_EN_MASK BIT(0)
#define HDCP_ENC_EN(x) UPDATE(x, 0, 0)
#define HDMI_RX_HDCP_SETTINGS REG(0x00c4)
#define HDMI_RX_HDCP_SEED REG(0x00c8)
#define HDMI_RX_HDCP_BKSV1 REG(0x00cc)
#define HDMI_RX_HDCP_BKSV0 REG(0x00d0)
#define HDMI_RX_HDCP_KIDX REG(0x00d4)
#define HDMI_RX_HDCP_KEY1 REG(0x00d8)
#define HDMI_RX_HDCP_KEY0 REG(0x00dc)
#define HDMI_RX_HDCP_DBG REG(0x00e0)
#define HDMI_RX_HDCP_AKSV1 REG(0x00e4)
#define HDMI_RX_HDCP_AKSV0 REG(0x00e8)
#define HDMI_RX_HDCP_AN1 REG(0x00ec)
#define HDMI_RX_HDCP_AN0 REG(0x00f0)
#define HDMI_RX_HDCP_EESS_WOO REG(0x00f4)
#define HDMI_RX_HDCP_I2C_TIMEOUT REG(0x00f8)
#define HDMI_RX_HDCP_STS REG(0x00fc)
#define HDMI_RX_MD_HCTRL1 REG(0x0140)
#define HACT_PIX_ITH_MASK GENMASK(10, 8)
#define HACT_PIX_ITH(x) UPDATE(x, 10, 8)
#define HACT_PIX_SRC_MASK BIT(5)
#define HACT_PIX_SRC(x) UPDATE(x, 5, 5)
#define HTOT_PIX_SRC_MASK BIT(4)
#define HTOT_PIX_SRC(x) UPDATE(x, 4, 4)
#define HDMI_RX_MD_HCTRL2 REG(0x0144)
#define HS_CLK_ITH_MASK GENMASK(14, 12)
#define HS_CLK_ITH(x) UPDATE(x, 14, 12)
#define HTOT32_CLK_ITH_MASK GENMASK(9, 8)
#define HTOT32_CLK_ITH(x) UPDATE(x, 9, 8)
#define VS_ACT_TIME_MASK BIT(5)
#define VS_ACT_TIME(x) UPDATE(x, 5, 5)
#define HS_ACT_TIME_MASK GENMASK(4, 3)
#define HS_ACT_TIME(x) UPDATE(x, 4, 3)
#define H_START_POS_MASK GENMASK(1, 0)
#define H_START_POS(x) UPDATE(x, 1, 0)
#define HDMI_RX_MD_HT0 REG(0x0148)
#define HDMI_RX_MD_HT1 REG(0x014c)
#define HDMI_RX_MD_HACT_PX REG(0x0150)
#define HDMI_RX_MD_HACT_RSV REG(0x0154)
#define HDMI_RX_MD_VCTRL REG(0x0158)
#define V_OFFS_LIN_MODE_MASK BIT(4)
#define V_OFFS_LIN_MODE(x) UPDATE(x, 4, 4)
#define V_EDGE_MASK BIT(1)
#define V_EDGE(x) UPDATE(x, 1, 1)
#define V_MODE_MASK BIT(0)
#define V_MODE(x) UPDATE(x, 0, 0)
#define HDMI_RX_MD_VSC REG(0x015c)
#define HDMI_RX_MD_VTC REG(0x0160)
#define HDMI_RX_MD_VOL REG(0x0164)
#define HDMI_RX_MD_VAL REG(0x0168)
#define HDMI_RX_MD_VTH REG(0x016c)
#define VOFS_LIN_ITH_MASK GENMASK(11, 10)
#define VOFS_LIN_ITH(x) UPDATE(x, 11, 10)
#define VACT_LIN_ITH_MASK GENMASK(9, 8)
#define VACT_LIN_ITH(x) UPDATE(x, 9, 8)
#define VTOT_LIN_ITH_MASK GENMASK(7, 6)
#define VTOT_LIN_ITH(x) UPDATE(x, 7, 6)
#define VS_CLK_ITH_MASK GENMASK(5, 3)
#define VS_CLK_ITH(x) UPDATE(x, 5, 3)
#define VTOT_CLK_ITH_MASK GENMASK(2, 0)
#define VTOT_CLK_ITH(x) UPDATE(x, 2, 0)
#define HDMI_RX_MD_VTL REG(0x0170)
#define HDMI_RX_MD_IL_CTRL REG(0x0174)
#define HDMI_RX_MD_IL_SKEW REG(0x0178)
#define HDMI_RX_MD_IL_POL REG(0x017c)
#define FAFIELDDET_EN_MASK BIT(2)
#define FAFIELDDET_EN(x) UPDATE(x, 2, 2)
#define FIELD_POL_MODE_MASK GENMASK(1, 0)
#define FIELD_POL_MODE(x) UPDATE(x, 1, 0)
#define HDMI_RX_MD_STS REG(0x0180)
#define HDMI_RX_AUD_CTRL REG(0x0200)
#define HDMI_RX_AUD_PLL_CTRL REG(0x0208)
#define PLL_LOCK_TOGGLE_DIV_MASK GENMASK(27, 24)
#define PLL_LOCK_TOGGLE_DIV(x) UPDATE(x, 27, 24)
#define HDMI_RX_AUD_CLK_CTRL REG(0x0214)
#define CTS_N_REF_MASK BIT(4)
#define CTS_N_REF(x) UPDATE(x, 4, 4)
#define HDMI_RX_AUD_CLK_STS REG(0x023c)
#define HDMI_RX_AUD_FIFO_CTRL REG(0x0240)
#define AFIF_SUBPACKET_DESEL_MASK GENMASK(27, 24)
#define AFIF_SUBPACKET_DESEL(x) UPDATE(x, 27, 24)
#define AFIF_SUBPACKETS_MASK BIT(16)
#define AFIF_SUBPACKETS(x) UPDATE(x, 16, 16)
#define MSA_CHANNEL_DESELECT BIT(24)
#define HDMI_RX_AUD_FIFO_TH REG(0x0244)
#define AFIF_TH_START_MASK GENMASK(26, 18)
#define AFIF_TH_START(x) UPDATE(x, 26, 18)
#define AFIF_TH_MAX_MASK GENMASK(17, 9)
#define AFIF_TH_MAX(x) UPDATE(x, 17, 9)
#define AFIF_TH_MIN_MASK GENMASK(8, 0)
#define AFIF_TH_MIN(x) UPDATE(x, 8, 0)
#define HDMI_RX_AUD_FIFO_FILL_S REG(0x0248)
#define HDMI_RX_AUD_FIFO_CLR_MM REG(0x024c)
#define HDMI_RX_AUD_FIFO_FILLSTS REG(0x0250)
#define HDMI_RX_AUD_CHEXTR_CTRL REG(0x0254)
#define AUD_LAYOUT_CTRL(x) UPDATE(x, 1, 0)
#define HDMI_RX_AUD_MUTE_CTRL REG(0x0258)
#define APPLY_INT_MUTE_MASK BIT(31)
#define APPLY_INT_MUTE(x) UPDATE(x, 31, 31)
#define APORT_SHDW_CTRL_MASK GENMASK(22, 21)
#define APORT_SHDW_CTRL(x) UPDATE(x, 22, 21)
#define AUTO_ACLK_MUTE_MASK GENMASK(20, 19)
#define AUTO_ACLK_MUTE(x) UPDATE(x, 20, 19)
#define AUD_MUTE_SPEED_MASK GENMASK(16, 10)
#define AUD_MUTE_SPEED(x) UPDATE(x, 16, 10)
#define AUD_AVMUTE_EN_MASK BIT(7)
#define AUD_AVMUTE_EN(x) UPDATE(x, 7, 7)
#define AUD_MUTE_SEL_MASK GENMASK(6, 5)
#define AUD_MUTE_SEL(x) UPDATE(x, 6, 5)
#define AUD_MUTE_MODE_MASK GENMASK(4, 3)
#define AUD_MUTE_MODE(x) UPDATE(x, 4, 3)
#define HDMI_RX_AUD_FIFO_FILLSTS1 REG(0x025c)
#define HDMI_RX_AUD_SAO_CTRL REG(0x0260)
#define I2S_LPCM_BPCUV_MASK BIT(11)
#define I2S_LPCM_BPCUV(x) UPDATE(x, 11, 11)
#define I2S_32_16_MASK BIT(0)
#define I2S_32_16(x) UPDATE(x, 0, 0)
#define HDMI_RX_AUD_PAO_CTRL REG(0x0264)
#define PAO_RATE_MASK GENMASK(17, 16)
#define PAO_RATE(x) UPDATE(x, 17, 16)
#define HDMI_RX_AUD_SPARE REG(0x0268)
#define HDMI_RX_AUD_FIFO_STS REG(0x027c)
#define HDMI_RX_AUDPLL_GEN_CTS REG(0x0280)
#define AUDPLL_CTS_MANUAL(x) UPDATE(x, 19, 0)
#define HDMI_RX_AUDPLL_GEN_N REG(0x0284)
#define AUDPLL_N_MANUAL(x) UPDATE(x, 19, 0)
#define HDMI_RX_AUDPLL_GEN_CTRL_RW1 REG(0x0288)
#define HDMI_RX_AUDPLL_GEN_CTRL_RW2 REG(0x028c)
#define HDMI_RX_AUDPLL_GEN_CTRL_W1 REG(0x0298)
#define HDMI_RX_AUDPLL_GEN_STS_RO1 REG(0x02a0)
#define HDMI_RX_AUDPLL_GEN_STS_RO2 REG(0x02a4)
#define HDMI_RX_AUDPLL_SC_NDIVCTSTH REG(0x02a8)
#define HDMI_RX_AUDPLL_SC_CTS REG(0x02ac)
#define HDMI_RX_AUDPLL_SC_N REG(0x02b0)
#define HDMI_RX_AUDPLL_SC_CTRL REG(0x02b4)
#define HDMI_RX_AUDPLL_SC_STS1 REG(0x02b8)
#define HDMI_RX_AUDPLL_SC_STS2 REG(0x02bc)
#define HDMI_RX_SNPS_PHYG3_CTRL REG(0x02c0)
#define PORTSELECT_MASK GENMASK(3, 2)
#define PORTSELECT(x) UPDATE(x, 3, 2)
#define HDMI_RX_I2CM_PHYG3_SLAVE REG(0x02c4)
#define HDMI_RX_I2CM_PHYG3_ADDRESS REG(0x02c8)
#define HDMI_RX_I2CM_PHYG3_DATAO REG(0x02cc)
#define HDMI_RX_I2CM_PHYG3_DATAI REG(0x02d0)
#define HDMI_RX_I2CM_PHYG3_OPERATION REG(0x02d4)
#define HDMI_RX_I2CM_PHYG3_MODE REG(0x02d8)
#define HDMI_RX_I2CM_PHYG3_SOFTRST REG(0x02dc)
#define HDMI_RX_I2CM_PHYG3_SS_CNTS REG(0x02e0)
#define HDMI_RX_I2CM_PHYG3_FS_HCNT REG(0x02e4)
#define HDMI_RX_JTAG_CONF REG(0x02ec)
#define HDMI_RX_JTAG_TAP_TCLK REG(0x02f0)
#define HDMI_RX_JTAG_TAP_IN REG(0x02f4)
#define HDMI_RX_JTAG_TAP_OUT REG(0x02f8)
#define HDMI_RX_JTAG_ADDR REG(0x02fc)
#define HDMI_RX_PDEC_CTRL REG(0x0300)
#define PFIFO_SCORE_FILTER_EN BIT(31)
#define PFIFO_SCORE_HDP_IF BIT(29)
#define PFIFO_SCORE_AMP_IF BIT(28)
#define PFIFO_SCORE_NTSCVBI_IF BIT(27)
#define PFIFO_SCORE_MPEGS_IF BIT(26)
#define PFIFO_SCORE_AUD_IF BIT(25)
#define PFIFO_SCORE_SPD_IF BIT(24)
#define PFIFO_SCORE_AVI_IF BIT(23)
#define PFIFO_SCORE_VS_IF BIT(22)
#define PFIFO_SCORE_GMTP BIT(21)
#define PFIFO_SCORE_ISRC2 BIT(20)
#define PFIFO_SCORE_ISRC1 BIT(19)
#define PFIFO_SCORE_ACP BIT(18)
#define PFIFO_SCORE_GCP BIT(17)
#define PFIFO_SCORE_ACR BIT(16)
#define GCP_GLOBAVMUTE BIT(15)
#define PD_FIFO_WE BIT(4)
#define PDEC_BCH_EN BIT(0)
#define HDMI_RX_PDEC_FIFO_CFG REG(0x0304)
#define PD_FIFO_TH_START_MASK GENMASK(29, 20)
#define PD_FIFO_TH_START(x) UPDATE(x, 29, 20)
#define PD_FIFO_TH_MAX_MASK GENMASK(19, 10)
#define PD_FIFO_TH_MAX(x) UPDATE(x, 19, 10)
#define PD_FIFO_TH_MIN_MASK GENMASK(9, 0)
#define PD_FIFO_TH_MIN(x) UPDATE(x, 9, 0)
#define HDMI_RX_PDEC_FIFO_STS REG(0x0308)
#define HDMI_RX_PDEC_FIFO_DATA REG(0x030c)
#define HDMI_RX_PDEC_AUDIODET_CTRL REG(0x0310)
#define AUDIODET_THRESHOLD_MASK GENMASK(13, 9)
#define AUDIODET_THRESHOLD(x) UPDATE(x, 13, 9)
#define HDMI_RX_PDEC_DBG_ACP REG(0x031c)
#define HDMI_RX_PDEC_DBG_ERR_CORR REG(0x0320)
#define HDMI_RX_PDEC_FIFO_STS1 REG(0x0324)
#define HDMI_RX_PDEC_ACRM_CTRL REG(0x0330)
#define DELTACTS_IRQTRIG_MASK GENMASK(4, 2)
#define DELTACTS_IRQTRIG(x) UPDATE(x, 4, 2)
#define HDMI_RX_PDEC_ACRM_MAX REG(0x0334)
#define HDMI_RX_PDEC_ACRM_MIN REG(0x0338)
#define HDMI_RX_PDEC_ERR_FILTER REG(0x033c)
#define HDMI_RX_PDEC_ASP_CTRL REG(0x0340)
#define HDMI_RX_PDEC_ASP_ERR REG(0x0344)
#define HDMI_RX_PDEC_STS REG(0x0360)
#define HDMI_RX_PDEC_AUD_STS REG(0x0364)
#define HDMI_RX_PDEC_VSI_PAYLOAD0 REG(0x0368)
#define HDMI_RX_PDEC_VSI_PAYLOAD1 REG(0x036c)
#define HDMI_RX_PDEC_VSI_PAYLOAD2 REG(0x0370)
#define HDMI_RX_PDEC_VSI_PAYLOAD3 REG(0x0374)
#define HDMI_RX_PDEC_VSI_PAYLOAD4 REG(0x0378)
#define HDMI_RX_PDEC_VSI_PAYLOAD5 REG(0x037c)
#define HDMI_RX_PDEC_GCP_AVMUTE REG(0x0380)
#define PKTDEC_GCP_CD_MASK GENMASK(7, 4)
#define HDMI_RX_PDEC_ACR_CTS REG(0x0390)
#define HDMI_RX_PDEC_ACR_N REG(0x0394)
#define HDMI_RX_PDEC_AVI_HB REG(0x03a0)
#define HDMI_RX_PDEC_AVI_PB REG(0x03a4)
#define VID_IDENT_CODE_VIC7 BIT(31)
#define VID_IDENT_CODE GENMASK(30, 24)
#define VIDEO_FORMAT GENMASK(6, 5)
#define HDMI_RX_PDEC_AVI_TBB REG(0x03a8)
#define HDMI_RX_PDEC_AVI_LRB REG(0x03ac)
#define HDMI_RX_PDEC_AIF_CTRL REG(0x03c0)
#define FC_LFE_EXCHG BIT(18)
#define HDMI_RX_PDEC_AIF_HB REG(0x03c4)
#define HDMI_RX_PDEC_AIF_PB0 REG(0x03c8)
#define HDMI_RX_PDEC_AIF_PB1 REG(0x03cc)
#define HDMI_RX_PDEC_GMD_HB REG(0x03d0)
#define HDMI_RX_PDEC_GMD_PB REG(0x03d4)
#define HDMI_RX_PDEC_VSI_ST0 REG(0x03e0)
#define HDMI_RX_PDEC_VSI_ST1 REG(0x03e4)
#define HDMI_RX_PDEC_VSI_PB0 REG(0x03e8)
#define HDMI_RX_PDEC_VSI_PB1 REG(0x03ec)
#define HDMI_RX_PDEC_VSI_PB2 REG(0x03f0)
#define HDMI_RX_PDEC_VSI_PB3 REG(0x03f4)
#define HDMI_RX_PDEC_VSI_PB4 REG(0x03f8)
#define HDMI_RX_PDEC_VSI_PB5 REG(0x03fc)
#define HDMI_RX_CEAVID_CONFIG REG(0x0400)
#define HDMI_RX_CEAVID_3DCONFIG REG(0x0404)
#define HDMI_RX_CEAVID_HCONFIG_LO REG(0x0408)
#define HDMI_RX_CEAVID_HCONFIG_HI REG(0x040c)
#define HDMI_RX_CEAVID_VCONFIG_LO REG(0x0410)
#define HDMI_RX_CEAVID_VCONFIG_HI REG(0x0414)
#define HDMI_RX_CEAVID_STATUS REG(0x0418)
#define HDMI_RX_PDEC_AMP_HB REG(0x0480)
#define HDMI_RX_PDEC_AMP_PAYLOAD0 REG(0x0484)
#define HDMI_RX_PDEC_AMP_PAYLOAD1 REG(0x0488)
#define HDMI_RX_PDEC_AMP_PAYLOAD2 REG(0x048c)
#define HDMI_RX_PDEC_AMP_PAYLOAD3 REG(0x0490)
#define HDMI_RX_PDEC_AMP_PAYLOAD4 REG(0x0494)
#define HDMI_RX_PDEC_AMP_PAYLOAD5 REG(0x0498)
#define HDMI_RX_PDEC_AMP_PAYLOAD6 REG(0x049c)
#define HDMI_RX_PDEC_NTSCVBI_HB REG(0x04a0)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0 REG(0x04a4)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1 REG(0x04a8)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2 REG(0x04ac)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3 REG(0x04b0)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4 REG(0x04b4)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5 REG(0x04b8)
#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6 REG(0x04bc)
#define HDMI_RX_PDEC_DRM_HB REG(0x04c0)
#define HDMI_RX_PDEC_DRM_PAYLOAD0 REG(0x04c4)
#define HDMI_RX_PDEC_DRM_PAYLOAD1 REG(0x04c8)
#define HDMI_RX_PDEC_DRM_PAYLOAD2 REG(0x04cc)
#define HDMI_RX_PDEC_DRM_PAYLOAD3 REG(0x04d0)
#define HDMI_RX_PDEC_DRM_PAYLOAD4 REG(0x04d4)
#define HDMI_RX_PDEC_DRM_PAYLOAD5 REG(0x04d8)
#define HDMI_RX_PDEC_DRM_PAYLOAD6 REG(0x04dc)
#define HDMI_RX_MHLMODE_CTRL REG(0x0500)
#define HDMI_RX_CDSENSE_STATUS REG(0x0504)
#define HDMI_RX_DESERFIFO_CTRL REG(0x0508)
#define HDMI_RX_DESER_INTTRSHCTRL REG(0x050c)
#define HDMI_RX_DESER_INTCNTCTRL REG(0x0510)
#define HDMI_RX_DESER_INTCNT REG(0x0514)
#define HDMI_RX_HDCP_RPT_CTRL REG(0x0600)
#define HDMI_RX_HDCP_RPT_BSTATUS REG(0x0604)
#define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL REG(0x0608)
#define HDMI_RX_HDCP_RPT_KSVFIFO1 REG(0x060c)
#define HDMI_RX_HDCP_RPT_KSVFIFO0 REG(0x0610)
#define HDMI_RX_HDMI20_CONTROL REG(0x0800)
#define HDMI_RX_SCDC_I2CCONFIG REG(0x0804)
#define I2CSPIKESUPPR_MASK GENMASK(25, 24)
#define I2CSPIKESUPPR(x) UPDATE(x, 25, 24)
#define HDMI_RX_SCDC_CONFIG REG(0x0808)
#define HDMI_RX_CHLOCK_CONFIG REG(0x080c)
#define CHLOCKMAXER_MASK GENMASK(29, 20)
#define CHLOCKMAXER(x) UPDATE(x, 29, 20)
#define MILISECTIMERLIMIT_MASK GENMASK(15, 0)
#define MILISECTIMERLIMIT(x) UPDATE(x, 15, 0)
#define HDMI_RX_HDCP22_CONTROL REG(0x081c)
#define HDMI_RX_SCDC_REGS0 REG(0x0820)
#define HDMI_RX_SCDC_REGS1 REG(0x0824)
#define HDMI_RX_SCDC_REGS2 REG(0x0828)
#define HDMI_RX_SCDC_REGS3 REG(0x082c)
#define HDMI_RX_SCDC_MANSPEC0 REG(0x0840)
#define HDMI_RX_SCDC_MANSPEC1 REG(0x0844)
#define HDMI_RX_SCDC_MANSPEC2 REG(0x0848)
#define HDMI_RX_SCDC_MANSPEC3 REG(0x084c)
#define HDMI_RX_SCDC_MANSPEC4 REG(0x0850)
#define HDMI_RX_SCDC_WRDATA0 REG(0x0860)
#define MANUFACTUREROUI_MASK GENMASK(31, 8)
#define MANUFACTUREROUI(x) UPDATE(x, 31, 8)
#define SINKVERSION_MASK GENMASK(7, 0)
#define SINKVERSION(x) UPDATE(x, 7, 0)
#define HDMI_RX_SCDC_WRDATA1 REG(0x0864)
#define HDMI_RX_SCDC_WRDATA2 REG(0x0868)
#define HDMI_RX_SCDC_WRDATA3 REG(0x086c)
#define HDMI_RX_SCDC_WRDATA4 REG(0x0870)
#define HDMI_RX_SCDC_WRDATA5 REG(0x0874)
#define HDMI_RX_SCDC_WRDATA6 REG(0x0878)
#define HDMI_RX_SCDC_WRDATA7 REG(0x087c)
#define HDMI_RX_HDMI20_STATUS REG(0x08e0)
#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN REG(0x08e8)
#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT REG(0x08ec)
#define HDMI_RX_HDCP2_ESM_P0_GPIO_IN REG(0x08f0)
#define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT REG(0x08f4)
#define HDMI_RX_HDCP22_STATUS REG(0x08fc)
#define HDMI_RX_HDMI2_IEN_CLR REG(0x0f60)
#define HDMI_RX_HDMI2_IEN_SET REG(0x0f64)
#define HDMI_RX_HDMI2_ISTS REG(0x0f68)
#define HDMI_RX_HDMI2_IEN REG(0x0f6c)
#define HDMI_RX_HDMI2_ICLR REG(0x0f70)
#define HDMI_RX_HDMI2_ISET REG(0x0f74)
#define HDMI_RX_PDEC_IEN_CLR REG(0x0f78)
#define HDMI_RX_PDEC_IEN_SET REG(0x0f7c)
#define HDMI_RX_PDEC_ISTS REG(0x0f80)
#define HDMI_RX_PDEC_IEN REG(0x0f84)
#define HDMI_RX_PDEC_ICLR REG(0x0f88)
#define HDMI_RX_PDEC_ISET REG(0x0f8c)
#define HDMI_RX_AUD_CEC_IEN_CLR REG(0x0f90)
#define HDMI_RX_AUD_CEC_IEN_SET REG(0x0f94)
#define HDMI_RX_AUD_CEC_ISTS REG(0x0f98)
#define HDMI_RX_AUD_CEC_IEN REG(0x0f9c)
#define HDMI_RX_AUD_CEC_ICLR REG(0x0fa0)
#define HDMI_RX_AUD_CEC_ISET REG(0x0fa4)
#define HDMI_RX_AUD_FIFO_IEN_CLR REG(0x0fa8)
#define HDMI_RX_AUD_FIFO_IEN_SET REG(0x0fac)
#define HDMI_RX_AUD_FIFO_ISTS REG(0x0fb0)
#define HDMI_RX_AUD_FIFO_IEN REG(0x0fb4)
#define HDMI_RX_AUD_FIFO_ICLR REG(0x0fb8)
#define HDMI_RX_AUD_FIFO_ISET REG(0x0fbc)
#define HDMI_RX_MD_IEN_CLR REG(0x0fc0)
#define HDMI_RX_MD_IEN_SET REG(0x0fc4)
#define HDMI_RX_MD_ISTS REG(0x0fc8)
#define HDMI_RX_MD_IEN REG(0x0fcc)
#define HDMI_RX_MD_ICLR REG(0x0fd0)
#define HDMI_RX_MD_ISET REG(0x0fd4)
#define HDMI_RX_HDMI_IEN_CLR REG(0x0fd8)
#define HDMI_RX_HDMI_IEN_SET REG(0x0fdc)
#define HDCP_DKSET_DONE_ENCLR_MASK BIT(31)
#define HDCP_DKSET_DONE_ENCLR(x) UPDATE(x, 31, 31)
#define HDMI_RX_HDMI_ISTS REG(0x0fe0)
#define HDMI_RX_HDMI_IEN REG(0x0fe4)
#define HDMI_RX_HDMI_ICLR REG(0x0fe8)
#define HDMI_RX_HDMI_ISET REG(0x0fec)
#define HDMI_RX_DMI_SW_RST REG(0x0ff0)
#define HDMI_RX_DMI_DISABLE_IF REG(0x0ff4)
#define MAIN_ENABLE BIT(0)
#define MODET_ENABLE BIT(1)
#define HDMI_ENABLE BIT(2)
#define BUS_ENABLE BIT(3)
#define AUD_ENABLE BIT(4)
#define CEC_ENABLE BIT(5)
#define PIXEL_ENABLE BIT(6)
#define VID_ENABLE BIT(7)
#define TMDS_ENABLE_MASK BIT(16)
#define TMDS_ENABLE(x) UPDATE(x, 16, 16)
#define HDMI_RX_DMI_MODULE_ID_EXT REG(0x0ff8)
#define HDMI_RX_DMI_MODULE_ID REG(0x0ffc)
#define HDMI_RX_CEC_CTRL REG(0x1f00)
#define HDMI_RX_CEC_MASK REG(0x1f08)
#define HDMI_RX_CEC_ADDR_L REG(0x1f14)
#define HDMI_RX_CEC_ADDR_H REG(0x1f18)
#define HDMI_RX_CEC_TX_CNT REG(0x1f1c)
#define HDMI_RX_CEC_RX_CNT REG(0x1f20)
#define HDMI_RX_CEC_TX_DATA_0 REG(0x1f40)
#define HDMI_RX_CEC_TX_DATA_1 REG(0x1f44)
#define HDMI_RX_CEC_TX_DATA_2 REG(0x1f48)
#define HDMI_RX_CEC_TX_DATA_3 REG(0x1f4c)
#define HDMI_RX_CEC_TX_DATA_4 REG(0x1f50)
#define HDMI_RX_CEC_TX_DATA_5 REG(0x1f54)
#define HDMI_RX_CEC_TX_DATA_6 REG(0x1f58)
#define HDMI_RX_CEC_TX_DATA_7 REG(0x1f5c)
#define HDMI_RX_CEC_TX_DATA_8 REG(0x1f60)
#define HDMI_RX_CEC_TX_DATA_9 REG(0x1f64)
#define HDMI_RX_CEC_TX_DATA_10 REG(0x1f68)
#define HDMI_RX_CEC_TX_DATA_11 REG(0x1f6c)
#define HDMI_RX_CEC_TX_DATA_12 REG(0x1f70)
#define HDMI_RX_CEC_TX_DATA_13 REG(0x1f74)
#define HDMI_RX_CEC_TX_DATA_14 REG(0x1f78)
#define HDMI_RX_CEC_TX_DATA_15 REG(0x1f7c)
#define HDMI_RX_CEC_RX_DATA_0 REG(0x1f80)
#define HDMI_RX_CEC_RX_DATA_1 REG(0x1f84)
#define HDMI_RX_CEC_RX_DATA_2 REG(0x1f88)
#define HDMI_RX_CEC_RX_DATA_3 REG(0x1f8c)
#define HDMI_RX_CEC_RX_DATA_4 REG(0x1f90)
#define HDMI_RX_CEC_RX_DATA_5 REG(0x1f94)
#define HDMI_RX_CEC_RX_DATA_6 REG(0x1f98)
#define HDMI_RX_CEC_RX_DATA_7 REG(0x1f9c)
#define HDMI_RX_CEC_RX_DATA_8 REG(0x1fa0)
#define HDMI_RX_CEC_RX_DATA_9 REG(0x1fa4)
#define HDMI_RX_CEC_RX_DATA_10 REG(0x1fa8)
#define HDMI_RX_CEC_RX_DATA_11 REG(0x1fac)
#define HDMI_RX_CEC_RX_DATA_12 REG(0x1fb0)
#define HDMI_RX_CEC_RX_DATA_13 REG(0x1fb4)
#define HDMI_RX_CEC_RX_DATA_14 REG(0x1fb8)
#define HDMI_RX_CEC_RX_DATA_15 REG(0x1fbc)
#define HDMI_RX_CEC_LOCK REG(0x1fc0)
#define HDMI_RX_CEC_WAKEUPCTRL REG(0x1fc4)
#define HDMI_RX_CBUSSWRESETREQ REG(0x3000)
#define HDMI_RX_CBUSENABLEIF REG(0x3004)
#define HDMI_RX_CB_LOCKONCLOCK_STS REG(0x3010)
#define HDMI_RX_CB_LOCKONCLOCKCLR REG(0x3014)
#define HDMI_RX_CBUSIOCTRL REG(0x3020)
#define HDMI_RX_DD_CTRL REG(0x3040)
#define HDMI_RX_DD_OP_CTRL REG(0x3044)
#define HDMI_RX_DD_STS REG(0x3048)
#define HDMI_RX_DD_BYPASS_EN REG(0x304c)
#define HDMI_RX_DD_BYPASS_CTRL REG(0x3050)
#define HDMI_RX_DD_BYPASS_CBUS REG(0x3054)
#define HDMI_RX_LL_TXPCKFIFO REG(0x3080)
#define HDMI_RX_LL_RXPCKFIFO_RD_CLR REG(0x3084)
#define HDMI_RX_LL_RXPCKFIFO_A REG(0x3088)
#define HDMI_RX_LL_RXPCKFIFO_B REG(0x308c)
#define HDMI_RX_LL_TXPCKCTRL_0 REG(0x3090)
#define HDMI_RX_LL_TXPCKCTRL_1 REG(0x3094)
#define HDMI_RX_LL_PCKFIFO_STS REG(0x309c)
#define HDMI_RX_LL_RXPCKCTRL_0 REG(0x30a0)
#define HDMI_RX_LL_RXPCKCTRL_1 REG(0x30a4)
#define HDMI_RX_LL_INTTRSHLDCTRL REG(0x30b0)
#define HDMI_RX_LL_INTCNTCTRL REG(0x30b4)
#define HDMI_RX_LL_INTCNT_0 REG(0x30b8)
#define HDMI_RX_LL_INTCNT_1 REG(0x30bc)
#define HDMI_RX_CBHDCP_OPCTRL REG(0x3100)
#define HDMI_RX_CBHDCP_WDATA_0 REG(0x3104)
#define HDMI_RX_CBHDCP_WDATA_1 REG(0x3108)
#define HDMI_RX_CBHDCP_RDATA_0 REG(0x310c)
#define HDMI_RX_CBHDCP_RDATA_1 REG(0x3110)
#define HDMI_RX_CBHDCP_STATUS REG(0x3114)
#define HDMI_RX_CBHDCP_DDC_REPORT REG(0x3118)
#define HDMI_RX_ISTAT_CB_DD REG(0x3200)
#define HDMI_RX_IMASK_CB_DD REG(0x3204)
#define HDMI_RX_IFORCE_CB_DD REG(0x3208)
#define HDMI_RX_ICLEAR_CB_DD REG(0x320c)
#define HDMI_RX_IMUTE_CB_DD REG(0x3210)
#define HDMI_RX_ISTAT_CB_LL REG(0x3220)
#define HDMI_RX_IMASK_CB_LL REG(0x3224)
#define HDMI_RX_IFORCE_CB_LL REG(0x3228)
#define HDMI_RX_ICLEAR_CB_LL REG(0x322c)
#define HDMI_RX_IMUTE_CB_LL REG(0x3230)
#define HDMI_RX_ISTAT_CB_HDCP REG(0x3240)
#define HDMI_RX_IMASK_CB_HDCP REG(0x3244)
#define HDMI_RX_IFORCE_CB_HDCP REG(0x3248)
#define HDMI_RX_ICLEAR_CB_HDCP REG(0x324c)
#define HDMI_RX_IMUTE_CB_HDCP REG(0x3250)
#define HDMI_RX_ISTAT_CB_MCTRL REG(0x3260)
#define HDMI_RX_IMASK_CB_MCTRL REG(0x3264)
#define HDMI_RX_IFORCE_CB_MCTRL REG(0x3268)
#define HDMI_RX_ICLEAR_CB_MCTRL REG(0x326c)
#define HDMI_RX_IMUTE_CB_MCTRL REG(0x3270)
#define HDMI_RX_IMASTER_MUTE_CB REG(0x32e0)
#define HDMI_RX_IVECTOR_INDEX_CB REG(0x32e4)
#define HDMI_RX_MAX_REGISTER HDMI_RX_IVECTOR_INDEX_CB
struct rk628_hdmirx {
struct drm_bridge base;
struct drm_bridge *bridge;
struct device *dev;
struct regmap *regmap;
struct regmap *grf;
struct phy *phy;
struct clk *pclk;
struct clk *cec_clk;
struct clk *aud_clk;
struct clk *imodet_clk;
struct reset_control *hdmirx;
struct reset_control *hdmirx_pon;
struct rk628 *parent;
struct drm_display_mode mode;
};
static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_TIMER_CTRL),
regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERD_STS),
regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_STS),
regmap_reg_range(HDMI_RX_PDEC_ACRM_CTRL, HDMI_RX_PDEC_ASP_ERR),
regmap_reg_range(HDMI_RX_PDEC_AVI_HB, HDMI_RX_PDEC_AVI_LRB),
regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_GMD_PB),
regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS3),
regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA7),
regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
};
static const struct regmap_access_table rk628_hdmirx_readable_table = {
.yes_ranges = rk628_hdmirx_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
};
static const struct regmap_config rk628_hdmirx_regmap_config = {
.name = "hdmirx",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = HDMI_RX_MAX_REGISTER,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.rd_table = &rk628_hdmirx_readable_table,
};
static inline struct rk628_hdmirx *bridge_to_hdmirx(struct drm_bridge *bridge)
{
return container_of(bridge, struct rk628_hdmirx, base);
}
static void rk628_hdmirx_ctrl_enable(struct rk628_hdmirx *hdmirx)
{
clk_prepare_enable(hdmirx->pclk);
clk_prepare_enable(hdmirx->aud_clk);
clk_prepare_enable(hdmirx->imodet_clk);
reset_control_deassert(hdmirx->hdmirx);
reset_control_deassert(hdmirx->hdmirx_pon);
regmap_update_bits(hdmirx->grf, GRF_SYSTEM_CON0,
SW_INPUT_MODE_MASK,
SW_INPUT_MODE(INPUT_MODE_HDMI));
regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000101ff);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000000);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0000017f);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI20_CONTROL, 0x10001f10);
regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x0016fff0);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0xf98a0190);
regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_MODE_RECOVER,
SPIKE_FILTER_EN_MASK | DVI_MODE_HYST_MASK |
HDMI_MODE_HYST_MASK | HDMI_MODE_MASK |
GB_DET_MASK | EESS_OESS_MASK | SEL_CTL01_MASK,
SPIKE_FILTER_EN(0) |
DVI_MODE_HYST(0) |
HDMI_MODE_HYST(0) |
HDMI_MODE(3) |
GB_DET(2) |
EESS_OESS(0) |
SEL_CTL01(1));
regmap_write(hdmirx->regmap, HDMI_RX_PDEC_CTRL, 0xbfff8011);
regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ASP_CTRL, 0x00000040);
regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_SYNC_CTRL,
VS_POL_ADJ_MODE_MASK | HS_POL_ADJ_MODE_MASK,
VS_POL_ADJ_MODE(2) | HS_POL_ADJ_MODE(2));
regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ERR_FILTER, 0x00000008);
regmap_update_bits(hdmirx->regmap, HDMI_RX_SCDC_I2CCONFIG,
I2CSPIKESUPPR_MASK, I2CSPIKESUPPR(1));
regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
regmap_write(hdmirx->regmap, HDMI_RX_SCDC_WRDATA0, 0xabcdef01);
regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_ERROR_PROTECT, 0x000d0c98);
regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL1, 0x00000010);
regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL2, 0x00001738);
regmap_write(hdmirx->regmap, HDMI_RX_MD_VCTRL, 0x00000012);
regmap_write(hdmirx->regmap, HDMI_RX_MD_VTH, 0x0000073a);
regmap_write(hdmirx->regmap, HDMI_RX_MD_IL_POL, 0x00000004);
regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ACRM_CTRL, 0x00000000);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_DCM_CTRL, 0x00040414);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_PCB_CTRL, 0x00100000);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_SETUP_CTRL, 0x0f000fff);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x00104260);
regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0x0f2d0eed);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000001);
udelay(400);
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
}
static void rk628_hdmirx_ctrl_disable(struct rk628_hdmirx *hdmirx)
{
reset_control_assert(hdmirx->hdmirx);
reset_control_assert(hdmirx->hdmirx_pon);
clk_disable_unprepare(hdmirx->pclk);
clk_disable_unprepare(hdmirx->aud_clk);
clk_disable_unprepare(hdmirx->imodet_clk);
}
static void rk628_hdmirx_bridge_enable(struct drm_bridge *bridge)
{
bool locked;
u32 value, i, hact, vact, bus_width, hdisplay, vdisplay;
struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
/* force 594m mode to yuv420 format */
if (hdmirx->mode.clock == 594000) {
/*
* bit30 is used to indicate whether it is
* yuv420 format
*/
bus_width = hdmirx->mode.clock | BIT(30);
hdisplay = hdmirx->mode.hdisplay / 2;
} else {
bus_width = hdmirx->mode.clock;
hdisplay = hdmirx->mode.hdisplay;
}
vdisplay = hdmirx->mode.vdisplay;
phy_set_bus_width(hdmirx->phy, bus_width);
phy_power_on(hdmirx->phy);
usleep_range(10*1000, 11*1000);
rk628_hdmirx_ctrl_enable(hdmirx);
/* if hdmirx ctrl unlock or get incorrect timing, reset ctrl and phy */
for (i = 0; i < 5; i++) {
usleep_range(100*1000, 110*1000);
regmap_read(hdmirx->regmap, HDMI_RX_SCDC_REGS1, &value);
dev_dbg(hdmirx->dev, "HDMI_RX_SCDC_REGS1:0x%x\n", value);
value = (value >> 8) & 0xf;
regmap_read(hdmirx->regmap, HDMI_RX_MD_HACT_PX, &hact);
regmap_read(hdmirx->regmap, HDMI_RX_MD_VAL, &vact);
hact = hact & 0xffff;
vact = vact & 0xffff;
dev_dbg(hdmirx->dev, "hact:%d,vact:%d\n", hact, vact);
if (value == 0xf && hact == hdisplay && vact == vdisplay)
locked = true;
else
locked = false;
if (!locked) {
rk628_hdmirx_ctrl_disable(hdmirx);
usleep_range(10*1000, 11*1000);
phy_power_off(hdmirx->phy);
usleep_range(10*1000, 11*1000);
phy_power_on(hdmirx->phy);
usleep_range(10*1000, 11*1000);
rk628_hdmirx_ctrl_enable(hdmirx);
} else {
/* hdmirx ctrl get correct timing, enable output */
regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF,
0x000001ff);
return;
}
}
dev_err(hdmirx->dev, "hdmirx channel can't lock!\n");
}
static void rk628_hdmirx_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
rk628_hdmirx_ctrl_disable(hdmirx);
phy_power_off(hdmirx->phy);
}
static int rk628_hdmirx_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
struct device *dev = hdmirx->dev;
int ret;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
NULL, &hdmirx->bridge);
if (ret) {
dev_err(dev, "failed to find next bridge\n");
return ret;
}
ret = drm_bridge_attach(bridge->encoder, hdmirx->bridge, bridge, flags);
if (ret) {
dev_err(dev, "failed to attach bridge\n");
return ret;
}
return 0;
}
static void rk628_hdmirx_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
drm_mode_copy(&hdmirx->mode, adj);
}
static const struct drm_bridge_funcs rk628_hdmirx_bridge_funcs = {
.attach = rk628_hdmirx_bridge_attach,
.enable = rk628_hdmirx_bridge_enable,
.disable = rk628_hdmirx_bridge_disable,
.mode_set = rk628_hdmirx_bridge_mode_set,
};
static int rk628_hdmirx_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct platform_device_info pdevinfo;
struct rk628_hdmirx *hdmirx;
int ret, irq;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
hdmirx = devm_kzalloc(dev, sizeof(*hdmirx), GFP_KERNEL);
if (!hdmirx)
return -ENOMEM;
hdmirx->dev = dev;
hdmirx->parent = rk628;
platform_set_drvdata(pdev, hdmirx);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
hdmirx->grf = rk628->grf;
if (!hdmirx->grf)
return -ENODEV;
hdmirx->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(hdmirx->pclk)) {
ret = PTR_ERR(hdmirx->pclk);
dev_err(dev, "failed to get pclk: %d\n", ret);
return ret;
}
hdmirx->cec_clk = devm_clk_get(dev, "cec");
if (IS_ERR(hdmirx->cec_clk)) {
ret = PTR_ERR(hdmirx->cec_clk);
dev_err(dev, "failed to get cec clk: %d\n", ret);
return ret;
}
hdmirx->aud_clk = devm_clk_get(dev, "audio");
if (IS_ERR(hdmirx->aud_clk)) {
ret = PTR_ERR(hdmirx->aud_clk);
dev_err(dev, "failed to get audio clk: %d\n", ret);
return ret;
}
hdmirx->imodet_clk = devm_clk_get(dev, "imodet");
if (IS_ERR(hdmirx->imodet_clk)) {
ret = PTR_ERR(hdmirx->imodet_clk);
dev_err(dev, "failed to get imodet clk: %d\n", ret);
return ret;
}
hdmirx->hdmirx = of_reset_control_get(dev->of_node, "hdmirx");
if (IS_ERR(hdmirx->hdmirx)) {
ret = PTR_ERR(hdmirx->hdmirx);
DRM_DEV_ERROR(dev, "failed to get hdmirx control: %d\n", ret);
return ret;
}
hdmirx->hdmirx_pon = of_reset_control_get(dev->of_node, "hdmirx_pon");
if (IS_ERR(hdmirx->hdmirx_pon)) {
ret = PTR_ERR(hdmirx->hdmirx_pon);
DRM_DEV_ERROR(dev, "failed to get hdmirx_pon control: %d\n", ret);
return ret;
}
hdmirx->phy = devm_of_phy_get(dev, dev->of_node, NULL);
if (IS_ERR(hdmirx->phy)) {
ret = PTR_ERR(hdmirx->phy);
dev_err(dev, "failed to get phy: %d\n", ret);
return ret;
}
hdmirx->regmap = devm_regmap_init_i2c(rk628->client,
&rk628_hdmirx_regmap_config);
if (IS_ERR(hdmirx->regmap)) {
ret = PTR_ERR(hdmirx->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
hdmirx->base.funcs = &rk628_hdmirx_bridge_funcs;
hdmirx->base.of_node = dev->of_node;
drm_bridge_add(&hdmirx->base);
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.parent = dev;
pdevinfo.id = PLATFORM_DEVID_AUTO;
return 0;
}
static int rk628_hdmirx_remove(struct platform_device *pdev)
{
struct rk628_hdmirx *hdmirx = platform_get_drvdata(pdev);
drm_bridge_remove(&hdmirx->base);
return 0;
}
static const struct of_device_id rk628_hdmirx_of_match[] = {
{ .compatible = "rockchip,rk628-hdmirx", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_hdmirx_of_match);
static struct platform_driver rk628_hdmirx_driver = {
.driver = {
.name = "rk628-hdmirx",
.of_match_table = of_match_ptr(rk628_hdmirx_of_match),
},
.probe = rk628_hdmirx_probe,
.remove = rk628_hdmirx_remove,
};
module_platform_driver(rk628_hdmirx_driver);
MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 HDMI RX driver");
MODULE_LICENSE("GPL v2");

320
drivers/gpu/drm/rockchip/rk628/rk628_lvds.c
View File

@@ -1,320 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/media-bus-format.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/rk628.h>
#include <linux/phy/phy.h>
#include <drm/drm_of.h>
#include <drm/drm_atomic.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
enum lvds_format {
LVDS_FORMAT_VESA_24BIT,
LVDS_FORMAT_JEIDA_24BIT,
LVDS_FORMAT_JEIDA_18BIT,
LVDS_FORMAT_VESA_18BIT,
};
enum lvds_link_type {
LVDS_SINGLE_LINK,
LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
};
struct rk628_lvds {
struct drm_bridge base;
struct drm_connector connector;
struct drm_panel *panel;
struct drm_display_mode mode;
struct device *dev;
struct regmap *grf;
struct phy *phy;
struct rk628 *parent;
enum lvds_format format;
enum lvds_link_type link_type;
};
static inline struct rk628_lvds *bridge_to_lvds(struct drm_bridge *b)
{
return container_of(b, struct rk628_lvds, base);
}
static inline struct rk628_lvds *connector_to_lvds(struct drm_connector *c)
{
return container_of(c, struct rk628_lvds, connector);
}
static enum lvds_format rk628_lvds_get_format(u32 bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
return LVDS_FORMAT_JEIDA_24BIT;
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
return LVDS_FORMAT_VESA_18BIT;
case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
default:
return LVDS_FORMAT_VESA_24BIT;
}
}
static enum lvds_link_type rk628_lvds_get_link_type(struct rk628_lvds *lvds)
{
struct device *dev = lvds->dev;
const char *str;
int ret;
ret = of_property_read_string(dev->of_node, "rockchip,link-type", &str);
if (ret < 0)
return LVDS_SINGLE_LINK;
if (!strcmp(str, "dual-link-odd-even-pixels"))
return LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
else if (!strcmp(str, "dual-link-even-odd-pixels"))
return LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
else if (!strcmp(str, "dual-link-left-right-pixels"))
return LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS;
else if (!strcmp(str, "dual-link-right-left-pixels"))
return LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS;
else
return LVDS_SINGLE_LINK;
}
static struct drm_encoder *
rk628_lvds_connector_best_encoder(struct drm_connector *connector)
{
struct rk628_lvds *lvds = connector_to_lvds(connector);
return lvds->base.encoder;
}
static int rk628_lvds_connector_get_modes(struct drm_connector *connector)
{
struct rk628_lvds *lvds = connector_to_lvds(connector);
struct drm_display_info *info = &connector->display_info;
int num_modes = 0;
num_modes = drm_panel_get_modes(lvds->panel, connector);
if (info->num_bus_formats)
lvds->format = rk628_lvds_get_format(info->bus_formats[0]);
else
lvds->format = LVDS_FORMAT_VESA_24BIT;
return num_modes;
}
static const struct drm_connector_helper_funcs
rk628_lvds_connector_helper_funcs = {
.get_modes = rk628_lvds_connector_get_modes,
.best_encoder = rk628_lvds_connector_best_encoder,
};
static void rk628_lvds_connector_destroy(struct drm_connector *connector)
{
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs rk628_lvds_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = rk628_lvds_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static void rk628_lvds_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
const struct drm_display_mode *mode = &lvds->mode;
u32 val, bus_width;
int ret;
regmap_update_bits(lvds->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_LVDS));
switch (lvds->link_type) {
case LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(1);
regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
SW_SPLIT_EN, SW_SPLIT_EN);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
SW_LVDS_CON_DUAL_SEL(1);
regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
SW_SPLIT_EN, SW_SPLIT_EN);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_SINGLE_LINK:
default:
val = SW_LVDS_CON_CHASEL(0) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN;
break;
}
val |= SW_LVDS_CON_SELECT(lvds->format) |
SW_LVDS_CON_MSBSEL(0) |
SW_LVDS_CON_CLKINV(0);
regmap_write(lvds->grf, GRF_LVDS_TX_CON, val);
bus_width |= (mode->clock / 1000) << 8;
phy_set_bus_width(lvds->phy, bus_width);
ret = phy_set_mode(lvds->phy, PHY_MODE_LVDS);
if (ret) {
dev_err(lvds->dev, "failed to set phy mode: %d\n", ret);
return;
}
phy_power_on(lvds->phy);
drm_panel_prepare(lvds->panel);
drm_panel_enable(lvds->panel);
}
static void rk628_lvds_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
drm_panel_disable(lvds->panel);
drm_panel_unprepare(lvds->panel);
phy_power_off(lvds->phy);
}
static int rk628_lvds_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
struct drm_connector *connector = &lvds->connector;
struct drm_device *drm = bridge->dev;
int ret;
if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
return 0;
ret = drm_connector_init(drm, connector, &rk628_lvds_connector_funcs,
DRM_MODE_CONNECTOR_LVDS);
if (ret) {
dev_err(lvds->dev, "Failed to initialize connector with drm\n");
return ret;
}
drm_connector_helper_add(connector, &rk628_lvds_connector_helper_funcs);
drm_connector_attach_encoder(connector, bridge->encoder);
return 0;
}
static void rk628_lvds_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
drm_mode_copy(&lvds->mode, mode);
}
static const struct drm_bridge_funcs rk628_lvds_bridge_funcs = {
.attach = rk628_lvds_bridge_attach,
.enable = rk628_lvds_bridge_enable,
.disable = rk628_lvds_bridge_disable,
.mode_set = rk628_lvds_bridge_mode_set,
};
static int rk628_lvds_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_lvds *lvds;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
lvds = devm_kzalloc(dev, sizeof(*lvds), GFP_KERNEL);
if (!lvds)
return -ENOMEM;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
&lvds->panel, NULL);
if (ret)
return ret;
lvds->dev = dev;
lvds->parent = rk628;
lvds->grf = rk628->grf;
lvds->link_type = rk628_lvds_get_link_type(lvds);
platform_set_drvdata(pdev, lvds);
lvds->phy = devm_of_phy_get(dev, dev->of_node, NULL);
if (IS_ERR(lvds->phy)) {
ret = PTR_ERR(lvds->phy);
dev_err(dev, "failed to get phy: %d\n", ret);
return ret;
}
lvds->base.funcs = &rk628_lvds_bridge_funcs;
lvds->base.of_node = dev->of_node;
drm_bridge_add(&lvds->base);
return 0;
}
static int rk628_lvds_remove(struct platform_device *pdev)
{
struct rk628_lvds *lvds = platform_get_drvdata(pdev);
drm_bridge_remove(&lvds->base);
return 0;
}
static const struct of_device_id rk628_lvds_of_match[] = {
{ .compatible = "rockchip,rk628-lvds", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_lvds_of_match);
static struct platform_driver rk628_lvds_driver = {
.driver = {
.name = "rk628-lvds",
.of_match_table = of_match_ptr(rk628_lvds_of_match),
},
.probe = rk628_lvds_probe,
.remove = rk628_lvds_remove,
};
module_platform_driver(rk628_lvds_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 LVDS driver");
MODULE_LICENSE("GPL v2");

495
drivers/gpu/drm/rockchip/rk628/rk628_post_process.c
View File

@@ -1,495 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/rk628.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
#include <drm/drm_of.h>
enum rk628_mode_sync_pol {
MODE_FLAG_NSYNC,
MODE_FLAG_PSYNC,
};
struct rk628_post_process {
struct drm_bridge base;
struct drm_bridge *bridge;
struct drm_display_mode src_mode;
struct drm_display_mode dst_mode;
struct device *dev;
struct regmap *grf;
struct clk *sclk_vop;
struct clk *clk_rx_read;
struct reset_control *rstc_decoder;
struct reset_control *rstc_clk_rx;
struct reset_control *rstc_vop;
struct rk628 *parent;
int sync_pol;
};
static inline struct rk628_post_process *bridge_to_pp(struct drm_bridge *bridge)
{
return container_of(bridge, struct rk628_post_process, base);
}
static void calc_dsp_frm_hst_vst(const struct videomode *src,
const struct videomode *dst,
u32 *dsp_frame_hst, u32 *dsp_frame_vst)
{
u32 bp_in, bp_out;
u32 v_scale_ratio;
u64 t_frm_st;
u64 t_bp_in, t_bp_out, t_delta, tin;
u32 src_pixclock, dst_pixclock;
u32 dsp_htotal, src_htotal, src_vtotal;
src_pixclock = div_u64(1000000000000llu, src->pixelclock);
dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
src_htotal = src->hsync_len + src->hback_porch + src->hactive +
src->hfront_porch;
src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
src->vfront_porch;
dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
dst->hfront_porch;
bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
src->hsync_len + src->hback_porch;
bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
dst->hsync_len + dst->hback_porch;
t_bp_in = bp_in * src_pixclock;
t_bp_out = bp_out * dst_pixclock;
tin = src_vtotal * src_htotal * src_pixclock;
v_scale_ratio = src->vactive / dst->vactive;
if (v_scale_ratio <= 2)
t_delta = 5 * src_htotal * src_pixclock;
else
t_delta = 12 * src_htotal * src_pixclock;
if (t_bp_in + t_delta > t_bp_out)
t_frm_st = (t_bp_in + t_delta - t_bp_out);
else
t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
do_div(t_frm_st, src_pixclock);
*dsp_frame_hst = do_div(t_frm_st, src_htotal);
*dsp_frame_vst = t_frm_st;
}
static void rk628_post_process_scaler_init(struct rk628_post_process *pp,
const struct drm_display_mode *s,
const struct drm_display_mode *d)
{
struct videomode src, dst;
u32 dsp_frame_hst, dsp_frame_vst;
u32 scl_hor_mode, scl_ver_mode;
u32 scl_v_factor, scl_h_factor;
u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
u8 hor_down_mode = 0, ver_down_mode = 0;
drm_display_mode_to_videomode(s, &src);
drm_display_mode_to_videomode(d, &dst);
dsp_htotal = dst.hsync_len + dst.hback_porch + dst.hactive +
dst.hfront_porch;
dsp_vtotal = dst.vsync_len + dst.vback_porch + dst.vactive +
dst.vfront_porch;
dsp_hs_end = dst.hsync_len;
dsp_vs_end = dst.vsync_len;
dsp_hbor_end = dst.hsync_len + dst.hback_porch + dst.hactive;
dsp_hbor_st = dst.hsync_len + dst.hback_porch;
dsp_vbor_end = dst.vsync_len + dst.vback_porch + dst.vactive;
dsp_vbor_st = dst.vsync_len + dst.vback_porch;
dsp_hact_st = dsp_hbor_st + bor_left;
dsp_hact_end = dsp_hbor_end - bor_right;
dsp_vact_st = dsp_vbor_st + bor_up;
dsp_vact_end = dsp_vbor_end - bor_down;
calc_dsp_frm_hst_vst(&src, &dst, &dsp_frame_hst, &dsp_frame_vst);
dev_dbg(pp->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
dsp_frame_vst, dsp_frame_hst);
if (src.hactive > dst.hactive) {
scl_hor_mode = 2;
if (hor_down_mode == 0) {
if ((src.hactive - 1) / (dst.hactive - 1) > 2)
scl_h_factor = ((src.hactive - 1) << 14) /
(dst.hactive - 1);
else
scl_h_factor = ((src.hactive - 2) << 14) /
(dst.hactive - 1);
} else {
scl_h_factor = (dst.hactive << 16) /
(src.hactive - 1);
}
dev_dbg(pp->dev, "horizontal scale down\n");
} else if (src.hactive == dst.hactive) {
scl_hor_mode = 0;
scl_h_factor = 0;
dev_dbg(pp->dev, "horizontal no scale\n");
} else {
scl_hor_mode = 1;
scl_h_factor = ((src.hactive - 1) << 16) / (dst.hactive - 1);
dev_dbg(pp->dev, "horizontal scale up\n");
}
if (src.vactive > dst.vactive) {
scl_ver_mode = 2;
if (ver_down_mode == 0) {
if ((src.vactive - 1) / (dst.vactive - 1) > 2)
scl_v_factor = ((src.vactive - 1) << 14) /
(dst.vactive - 1);
else
scl_v_factor = ((src.vactive - 2) << 14) /
(dst.vactive - 1);
} else {
scl_v_factor = (dst.vactive << 16) /
(src.vactive - 1);
}
dev_dbg(pp->dev, "vertical scale down\n");
} else if (src.vactive == dst.vactive) {
scl_ver_mode = 0;
scl_v_factor = 0;
dev_dbg(pp->dev, "vertical no scale\n");
} else {
scl_ver_mode = 1;
scl_v_factor = ((src.vactive - 1) << 16) / (dst.vactive - 1);
dev_dbg(pp->dev, "vertical scale up\n");
}
regmap_update_bits(pp->grf, GRF_RGB_DEC_CON0,
SW_HRES_MASK, SW_HRES(src.hactive));
regmap_write(pp->grf, GRF_SCALER_CON0,
SCL_VER_DOWN_MODE(ver_down_mode) |
SCL_HOR_DOWN_MODE(hor_down_mode) |
SCL_VER_MODE(scl_ver_mode) | SCL_HOR_MODE(scl_hor_mode));
regmap_write(pp->grf, GRF_SCALER_CON1,
SCL_V_FACTOR(scl_v_factor) | SCL_H_FACTOR(scl_h_factor));
regmap_write(pp->grf, GRF_SCALER_CON2,
DSP_FRAME_VST(dsp_frame_vst) |
DSP_FRAME_HST(dsp_frame_hst));
regmap_write(pp->grf, GRF_SCALER_CON3,
DSP_HS_END(dsp_hs_end) | DSP_HTOTAL(dsp_htotal));
regmap_write(pp->grf, GRF_SCALER_CON4,
DSP_HACT_END(dsp_hact_end) | DSP_HACT_ST(dsp_hact_st));
regmap_write(pp->grf, GRF_SCALER_CON5,
DSP_VS_END(dsp_vs_end) | DSP_VTOTAL(dsp_vtotal));
regmap_write(pp->grf, GRF_SCALER_CON6,
DSP_VACT_END(dsp_vact_end) | DSP_VACT_ST(dsp_vact_st));
regmap_write(pp->grf, GRF_SCALER_CON7,
DSP_HBOR_END(dsp_hbor_end) | DSP_HBOR_ST(dsp_hbor_st));
regmap_write(pp->grf, GRF_SCALER_CON8,
DSP_VBOR_END(dsp_vbor_end) | DSP_VBOR_ST(dsp_vbor_st));
}
static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
struct drm_display_mode *src = &pp->src_mode;
struct drm_display_mode *dst = &pp->dst_mode;
u64 dst_rate, src_rate;
reset_control_assert(pp->rstc_decoder);
udelay(10);
reset_control_deassert(pp->rstc_decoder);
udelay(10);
clk_set_rate(pp->clk_rx_read, src->clock * 1000);
clk_prepare_enable(pp->clk_rx_read);
reset_control_assert(pp->rstc_clk_rx);
udelay(10);
reset_control_deassert(pp->rstc_clk_rx);
udelay(10);
src_rate = src->clock * 1000;
dst_rate = src_rate * dst->vdisplay * dst->htotal;
do_div(dst_rate, src->vdisplay * src->htotal);
do_div(dst_rate, 1000);
dst->clock = dst_rate;
clk_set_rate(pp->sclk_vop, dst->clock * 1000);
clk_prepare_enable(pp->sclk_vop);
reset_control_assert(pp->rstc_vop);
udelay(10);
reset_control_deassert(pp->rstc_vop);
udelay(10);
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
SW_VSYNC_POL(pp->sync_pol));
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
SW_HSYNC_POL(pp->sync_pol));
rk628_post_process_scaler_init(pp, src, dst);
}
static void rk628_post_process_bridge_post_disable(struct drm_bridge *bridge)
{
}
static void rk628_post_process_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(1));
}
static void rk628_post_process_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(0));
clk_disable_unprepare(pp->sclk_vop);
clk_disable_unprepare(pp->clk_rx_read);
}
static void rk628_post_process_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
struct rk628 *rk628 = pp->parent;
drm_mode_copy(&pp->src_mode, adj);
if (rk628->dst_mode_valid)
drm_mode_copy(&pp->dst_mode, &rk628->dst_mode);
else
drm_mode_copy(&pp->dst_mode, &pp->src_mode);
/* hdmirx 4k-60Hz mode only support yuv420 */
if (pp->src_mode.clock == 594000)
regmap_write(pp->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
}
static int rk628_post_process_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
struct device *dev = pp->dev;
int ret;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
NULL, &pp->bridge);
if (ret)
return ret;
ret = drm_bridge_attach(bridge->encoder, pp->bridge, bridge, flags);
if (ret) {
dev_err(dev, "failed to attach bridge\n");
return ret;
}
return 0;
}
static bool
rk628_post_process_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
if (pp->sync_pol == MODE_FLAG_NSYNC) {
adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
} else {
adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
}
return true;
}
static const struct drm_bridge_funcs rk628_post_process_bridge_funcs = {
.pre_enable = rk628_post_process_bridge_pre_enable,
.post_disable = rk628_post_process_bridge_post_disable,
.enable = rk628_post_process_bridge_enable,
.disable = rk628_post_process_bridge_disable,
.mode_set = rk628_post_process_bridge_mode_set,
.mode_fixup = rk628_post_process_bridge_mode_fixup,
.attach = rk628_post_process_bridge_attach,
};
/**
* rk628_scaler_add_src_mode - add source mode for scaler
* @rk628: parent device
* @connector: DRM connector
* If need scale, call the function at last of get_modes.
*/
int rk628_scaler_add_src_mode(struct rk628 *rk628,
struct drm_connector *connector)
{
struct drm_display_mode *pmode;
struct drm_display_mode *dst;
if (!rk628 || !connector)
return 0;
if (drm_mode_validate_driver(connector->dev, &rk628->src_mode) !=
MODE_OK)
return 0;
list_for_each_entry(pmode, &connector->probed_modes, head) {
if (pmode->type & DRM_MODE_TYPE_PREFERRED) {
drm_mode_copy(&rk628->dst_mode, pmode);
drm_mode_copy(pmode, &rk628->src_mode);
pmode->type |= DRM_MODE_TYPE_PREFERRED;
rk628->dst_mode_valid = true;
break;
}
}
if (rk628->dst_mode_valid) {
dst = drm_mode_duplicate(connector->dev, &rk628->dst_mode);
dst->type &= ~DRM_MODE_TYPE_PREFERRED;
drm_mode_probed_add(connector, dst);
return 1;
}
return 0;
}
EXPORT_SYMBOL(rk628_scaler_add_src_mode);
/**
* rk628_mode_copy - rk628 mode copy
* @rk628: parent device
* @dst: dst mode
* @src: src mode
* Call the function at mode_set, replace drm_mode_copy.
*/
void rk628_mode_copy(struct rk628 *rk628, struct drm_display_mode *dst,
const struct drm_display_mode *src)
{
if (rk628->dst_mode_valid)
drm_mode_copy(dst, &rk628->dst_mode);
else
drm_mode_copy(dst, src);
}
EXPORT_SYMBOL(rk628_mode_copy);
static int rk628_post_process_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_post_process *pp;
u32 bus_flags;
u32 val;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
if (!pp)
return -ENOMEM;
pp->dev = dev;
pp->grf = rk628->grf;
platform_set_drvdata(pdev, pp);
pp->parent = rk628;
pp->sclk_vop = devm_clk_get(dev, "sclk_vop");
if (IS_ERR(pp->sclk_vop)) {
ret = PTR_ERR(pp->sclk_vop);
dev_err(dev, "failed to get sclk: %d\n", ret);
return ret;
}
pp->clk_rx_read = devm_clk_get(dev, "rx_read");
if (IS_ERR(pp->clk_rx_read)) {
ret = PTR_ERR(pp->clk_rx_read);
dev_err(dev, "failed to get clk_rx_read: %d\n", ret);
return ret;
}
pp->rstc_decoder = of_reset_control_get(dev->of_node, "decoder");
if (IS_ERR(pp->rstc_decoder)) {
ret = PTR_ERR(pp->rstc_decoder);
dev_err(dev, "failed to get decoder reset: %d\n", ret);
return ret;
}
pp->rstc_clk_rx = of_reset_control_get(dev->of_node, "clk_rx");
if (IS_ERR(pp->rstc_clk_rx)) {
ret = PTR_ERR(pp->rstc_clk_rx);
dev_err(dev, "failed to get clk_rx reset: %d\n", ret);
return ret;
}
pp->rstc_vop = of_reset_control_get(dev->of_node, "vop");
if (IS_ERR(pp->rstc_vop)) {
ret = PTR_ERR(pp->rstc_vop);
dev_err(dev, "failed to get vop reset: %d\n", ret);
return ret;
}
ret = of_property_read_u32(dev->of_node, "mode-sync-pol", &val);
if (ret < 0)
pp->sync_pol = MODE_FLAG_PSYNC;
else
pp->sync_pol = (!val ? MODE_FLAG_NSYNC : MODE_FLAG_PSYNC);
pp->base.funcs = &rk628_post_process_bridge_funcs;
pp->base.of_node = dev->of_node;
drm_bridge_add(&pp->base);
of_get_drm_display_mode(dev->of_node, &rk628->src_mode, &bus_flags,
OF_USE_NATIVE_MODE);
return 0;
}
static int rk628_post_process_remove(struct platform_device *pdev)
{
struct rk628_post_process *pp = platform_get_drvdata(pdev);
drm_bridge_remove(&pp->base);
return 0;
}
static const struct of_device_id rk628_post_process_of_match[] = {
{ .compatible = "rockchip,rk628-post-process", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_post_process_of_match);
static struct platform_driver rk628_post_process_driver = {
.driver = {
.name = "rk628-post-process",
.of_match_table = of_match_ptr(rk628_post_process_of_match),
},
.probe = rk628_post_process_probe,
.remove = rk628_post_process_remove,
};
module_platform_driver(rk628_post_process_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 Post Process driver");
MODULE_LICENSE("GPL v2");

378
drivers/gpu/drm/rockchip/rk628/rk628_rgb.c
View File

@@ -1,378 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/rk628.h>
#include <linux/phy/phy.h>
#include <linux/reset.h>
#include <drm/drm_of.h>
#include <drm/drm_atomic.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
enum interface_type {
RGB_TX,
YUV_RX,
YUV_TX,
BT1120_RX,
BT1120_TX,
};
struct rk628_rgb {
struct drm_bridge base;
struct drm_connector connector;
struct drm_display_mode mode;
struct drm_panel *panel;
struct drm_bridge *bridge;
struct device *dev;
struct regmap *grf;
struct rk628 *parent;
struct clk *decclk;
struct reset_control *rstc;
bool dual_edge;
enum interface_type interface_type;
};
static inline struct rk628_rgb *bridge_to_rgb(struct drm_bridge *b)
{
return container_of(b, struct rk628_rgb, base);
}
static inline struct rk628_rgb *connector_to_rgb(struct drm_connector *c)
{
return container_of(c, struct rk628_rgb, connector);
}
static enum interface_type rk628_rgb_get_interface_type(struct rk628_rgb *rgb)
{
const struct device_node *of_node = rgb->dev->of_node;
if (of_device_is_compatible(of_node, "rockchip,rk628-yuv-rx"))
return YUV_RX;
else if (of_device_is_compatible(of_node, "rockchip,rk628-yuv-tx"))
return YUV_TX;
else if (of_device_is_compatible(of_node, "rockchip,rk628-bt1120-rx"))
return BT1120_RX;
else if (of_device_is_compatible(of_node, "rockchip,rk628-bt1120-tx"))
return BT1120_TX;
else
return RGB_TX;
}
static struct drm_encoder *
rk628_rgb_connector_best_encoder(struct drm_connector *connector)
{
struct rk628_rgb *rgb = connector_to_rgb(connector);
return rgb->base.encoder;
}
static int rk628_rgb_connector_get_modes(struct drm_connector *connector)
{
struct rk628_rgb *rgb = connector_to_rgb(connector);
return drm_panel_get_modes(rgb->panel, connector);
}
static const struct drm_connector_helper_funcs
rk628_rgb_connector_helper_funcs = {
.get_modes = rk628_rgb_connector_get_modes,
.best_encoder = rk628_rgb_connector_best_encoder,
};
static void rk628_rgb_connector_destroy(struct drm_connector *connector)
{
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs rk628_rgb_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = rk628_rgb_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static void rk628_bt1120_rx_enable(struct rk628_rgb *rgb)
{
const struct drm_display_mode *mode = &rgb->mode;
reset_control_assert(rgb->rstc);
udelay(10);
reset_control_deassert(rgb->rstc);
udelay(10);
clk_set_rate(rgb->decclk, mode->clock * 1000);
clk_prepare_enable(rgb->decclk);
if (rgb->dual_edge) {
regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
DEC_DUALEDGE_EN, DEC_DUALEDGE_EN);
regmap_write(rgb->grf,
GRF_BT1120_DCLK_DELAY_CON0, 0x10000000);
regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON1, 0);
} else
regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
DEC_DUALEDGE_EN, 0);
regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON1,
SW_SET_X_MASK, SW_SET_X(mode->hdisplay));
regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON2,
SW_SET_Y_MASK, SW_SET_Y(mode->vdisplay));
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_INPUT_MODE_MASK,
SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_BT1120));
regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
regmap_update_bits(rgb->grf, GRF_RGB_DEC_CON0,
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN,
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN);
}
static void rk628_bt1120_tx_enable(struct rk628_rgb *rgb)
{
u32 val = 0;
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_BT1120));
regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));
regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
if (rgb->dual_edge) {
val |= ENC_DUALEDGE_EN(1);
regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON0, 0x10000000);
regmap_write(rgb->grf, GRF_BT1120_DCLK_DELAY_CON1, 0);
}
val |= BT1120_UV_SWAP(1);
regmap_write(rgb->grf, GRF_RGB_ENC_CON, val);
}
static void rk628_rgb_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
switch (rgb->interface_type) {
case YUV_RX:
regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_INPUT_MODE_MASK,
SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_YUV));
break;
case YUV_TX:
regmap_write(rgb->grf, GRF_CSC_CTRL_CON, SW_R2Y_EN(1));
regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_YUV));
break;
case BT1120_RX:
rk628_bt1120_rx_enable(rgb);
break;
case BT1120_TX:
rk628_bt1120_tx_enable(rgb);
break;
case RGB_TX:
default:
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_RGB));
regmap_update_bits(rgb->grf, GRF_POST_PROC_CON,
SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
break;
}
if (rgb->panel) {
drm_panel_prepare(rgb->panel);
drm_panel_enable(rgb->panel);
}
}
static void rk628_rgb_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
if (rgb->panel) {
drm_panel_disable(rgb->panel);
drm_panel_unprepare(rgb->panel);
}
if (rgb->decclk)
clk_disable_unprepare(rgb->decclk);
if (rgb->rstc)
reset_control_assert(rgb->rstc);
}
static int rk628_rgb_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
struct drm_connector *connector = &rgb->connector;
struct drm_device *drm = bridge->dev;
struct device *dev = rgb->dev;
int ret;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
&rgb->panel, &rgb->bridge);
if (ret)
return ret;
if (rgb->interface_type == YUV_RX || rgb->interface_type == BT1120_RX) {
if (!rgb->bridge) {
dev_err(dev, "decoder failed to find bridge\n");
return -EPROBE_DEFER;
}
ret = drm_bridge_attach(bridge->encoder, rgb->bridge, bridge,
flags);
if (ret) {
dev_err(dev, "failed to attach bridge\n");
return ret;
}
} else {
if (rgb->bridge) {
ret = drm_bridge_attach(bridge->encoder, rgb->bridge,
bridge, flags);
if (ret) {
dev_err(dev, "failed to attach bridge\n");
return ret;
}
}
if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
return 0;
if (rgb->panel) {
ret = drm_connector_init(drm, connector,
&rk628_rgb_connector_funcs,
DRM_MODE_CONNECTOR_DPI);
if (ret) {
dev_err(dev,
"Failed to initialize connector with drm\n");
return ret;
}
drm_connector_helper_add(connector,
&rk628_rgb_connector_helper_funcs);
drm_connector_attach_encoder(connector,
bridge->encoder);
}
}
return 0;
}
static void rk628_rgb_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
drm_mode_copy(&rgb->mode, adj);
}
static const struct drm_bridge_funcs rk628_rgb_bridge_funcs = {
.attach = rk628_rgb_bridge_attach,
.enable = rk628_rgb_bridge_enable,
.disable = rk628_rgb_bridge_disable,
.mode_set = rk628_rgb_bridge_mode_set,
};
static int rk628_rgb_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_rgb *rgb;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
rgb = devm_kzalloc(dev, sizeof(*rgb), GFP_KERNEL);
if (!rgb)
return -ENOMEM;
rgb->dev = dev;
rgb->parent = rk628;
rgb->grf = rk628->grf;
rgb->interface_type = rk628_rgb_get_interface_type(rgb);
rgb->dual_edge = of_property_read_bool(dev->of_node, "dual-edge");
platform_set_drvdata(pdev, rgb);
if (rgb->interface_type == BT1120_RX) {
rgb->decclk = devm_clk_get(dev, "bt1120dec");
if (IS_ERR(rgb->decclk)) {
ret = PTR_ERR(rgb->decclk);
dev_err(dev, "failed to get dec clk: %d\n", ret);
return ret;
}
rgb->rstc = of_reset_control_get(dev->of_node, NULL);
if (IS_ERR(rgb->rstc)) {
ret = PTR_ERR(rgb->rstc);
dev_err(dev, "failed to get reset control: %d\n", ret);
return ret;
}
}
rgb->base.funcs = &rk628_rgb_bridge_funcs;
rgb->base.of_node = dev->of_node;
drm_bridge_add(&rgb->base);
return 0;
}
static int rk628_rgb_remove(struct platform_device *pdev)
{
struct rk628_rgb *rgb = platform_get_drvdata(pdev);
drm_bridge_remove(&rgb->base);
return 0;
}
static const struct of_device_id rk628_rgb_of_match[] = {
{ .compatible = "rockchip,rk628-rgb-tx", },
{ .compatible = "rockchip,rk628-yuv-rx", },
{ .compatible = "rockchip,rk628-yuv-tx", },
{ .compatible = "rockchip,rk628-bt1120-rx", },
{ .compatible = "rockchip,rk628-bt1120-tx", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_rgb_of_match);
static struct platform_driver rk628_rgb_driver = {
.driver = {
.name = "rk628-rgb",
.of_match_table = of_match_ptr(rk628_rgb_of_match),
},
.probe = rk628_rgb_probe,
.remove = rk628_rgb_remove,
};
module_platform_driver(rk628_rgb_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 RGB driver");
MODULE_LICENSE("GPL v2");

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1443,6 +1443,7 @@ static const struct vop_win_phy rk3366_lit_win0_data = {
.enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
.interlace_read = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 8),
.csc_mode = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x3, 10),
.rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
.dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
@@ -1626,6 +1627,7 @@ static const struct vop_win_phy px30_win23_data = {
.nformats = ARRAY_SIZE(formats_win_lite),
.gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
.csc_mode = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 2),
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),

2
drivers/input/sensors/accel/bma2xx.c
View File

@@ -2250,7 +2250,7 @@ static const struct i2c_device_id gsensor_bma2x2_id[] = {
static struct i2c_driver gsensor_bma2x2_driver = {
.probe = gsensor_bma2x2_probe,
.remove = gsensor_bma2x2_remove,
.remove = (void *)gsensor_bma2x2_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_bma2x2_id,
.driver = {

2
drivers/input/sensors/accel/da215s/da215s.c
View File

@@ -325,7 +325,7 @@ static const struct i2c_device_id gsensor_da215s_id[] = {
static struct i2c_driver gsensor_da215s_driver = {
.probe = gsensor_da215s_probe,
.remove = gsensor_da215s_remove,
.remove = (void *)gsensor_da215s_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_da215s_id,
.driver = {

2
drivers/input/sensors/accel/da223_cust.c
View File

@@ -881,7 +881,7 @@ static const struct i2c_device_id gsensor_mir3da_id[] = {
static struct i2c_driver gsensor_mir3da_driver = {
.probe = gsensor_mir3da_probe,
.remove = gsensor_mir3da_remove,
.remove = (void *)gsensor_mir3da_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mir3da_id,
.driver = {

2
drivers/input/sensors/accel/da228e/da228e.c
View File

@@ -326,7 +326,7 @@ static const struct i2c_device_id gsensor_da228e_id[] = {
static struct i2c_driver gsensor_da228e_driver = {
.probe = gsensor_da228e_probe,
.remove = gsensor_da228e_remove,
.remove = (void *)gsensor_da228e_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_da228e_id,
.driver = {

2
drivers/input/sensors/accel/dmard10.c
View File

@@ -435,7 +435,7 @@ static const struct i2c_device_id gsensor_dmard10_id[] = {
static struct i2c_driver gsensor_dmard10_driver = {
.probe = gsensor_dmard10_probe,
.remove = gsensor_dmard10_remove,
.remove = (void *)gsensor_dmard10_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_dmard10_id,
.driver = {

2
drivers/input/sensors/accel/iam20680_acc.c
View File

@@ -221,7 +221,7 @@ static const struct i2c_device_id gsensor_iam20680_id[] = {
static struct i2c_driver gsensor_iam20680_driver = {
.probe = gsensor_iam20680_probe,
.remove = gsensor_iam20680_remove,
.remove = (void *)gsensor_iam20680_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_iam20680_id,
.driver = {

2
drivers/input/sensors/accel/icm2060x_acc.c
View File

@@ -242,7 +242,7 @@ static const struct i2c_device_id gsensor_icm2060x_id[] = {
static struct i2c_driver gsensor_icm2060x_driver = {
.probe = gsensor_icm2060x_probe,
.remove = gsensor_icm2060x_remove,
.remove = (void *)gsensor_icm2060x_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_icm2060x_id,
.driver = {

2
drivers/input/sensors/accel/icm4260x_acc.c
View File

@@ -451,7 +451,7 @@ static const struct i2c_device_id gsensor_icm4260x_id[] = {
static struct i2c_driver gsensor_icm4260x_driver = {
.probe = gsensor_icm4260x_probe,
.remove = gsensor_icm4260x_remove,
.remove = (void *)gsensor_icm4260x_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_icm4260x_id,
.driver = {

2
drivers/input/sensors/accel/kxtik.c
View File

@@ -341,7 +341,7 @@ static const struct i2c_device_id gsensor_kxtik_id[] = {
static struct i2c_driver gsensor_kxtik_driver = {
.probe = gsensor_kxtik_probe,
.remove = gsensor_kxtik_remove,
.remove = (void *)gsensor_kxtik_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_kxtik_id,
.driver = {

2
drivers/input/sensors/accel/kxtj9.c
View File

@@ -314,7 +314,7 @@ static const struct i2c_device_id gsensor_kxtj9_id[] = {
static struct i2c_driver gsensor_kxtj9_driver = {
.probe = gsensor_kxtj9_probe,
.remove = gsensor_kxtj9_remove,
.remove = (void *)gsensor_kxtj9_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_kxtj9_id,
.driver = {

2
drivers/input/sensors/accel/lis3dh.c
View File

@@ -285,7 +285,7 @@ static const struct i2c_device_id gsensor_lis3dh_id[] = {
static struct i2c_driver gsensor_lis3dh_driver = {
.probe = gsensor_lis3dh_probe,
.remove = gsensor_lis3dh_remove,
.remove = (void *)gsensor_lis3dh_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_lis3dh_id,
.driver = {

2
drivers/input/sensors/accel/lsm303d.c
View File

@@ -344,7 +344,7 @@ static const struct i2c_device_id gsensor_lsm303d_id[] = {
static struct i2c_driver gsensor_lsm303d_driver = {
.probe = gsensor_lsm303d_probe,
.remove = gsensor_lsm303d_remove,
.remove = (void *)gsensor_lsm303d_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_lsm303d_id,
.driver = {

2
drivers/input/sensors/accel/lsm330_acc.c
View File

@@ -260,7 +260,7 @@ static const struct i2c_device_id gsensor_lsm330_id[] = {
static struct i2c_driver gsensor_lsm330_driver = {
.probe = gsensor_lsm330_probe,
.remove = gsensor_lsm330_remove,
.remove = (void *)gsensor_lsm330_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_lsm330_id,
.driver = {

2
drivers/input/sensors/accel/mc3230.c
View File

@@ -1331,7 +1331,7 @@ static const struct i2c_device_id gsensor_mc3230_id[] = {
static struct i2c_driver gsensor_mc3230_driver = {
.probe = gsensor_mc3230_probe,
.remove = gsensor_mc3230_remove,
.remove = (void *)gsensor_mc3230_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mc3230_id,
.driver = {

2
drivers/input/sensors/accel/mma7660.c
View File

@@ -240,7 +240,7 @@ static const struct i2c_device_id gsensor_mma7660_id[] = {
static struct i2c_driver gsensor_mma7660_driver = {
.probe = gsensor_mma7660_probe,
.remove = gsensor_mma7660_remove,
.remove = (void *)gsensor_mma7660_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mma7660_id,
.driver = {

2
drivers/input/sensors/accel/mma8452.c
View File

@@ -406,7 +406,7 @@ static const struct i2c_device_id gsensor_mma8452_id[] = {
static struct i2c_driver gsensor_mma8452_driver = {
.probe = gsensor_mma8452_probe,
.remove = gsensor_mma8452_remove,
.remove = (void *)gsensor_mma8452_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mma8452_id,
.driver = {

2
drivers/input/sensors/accel/mpu6500_acc.c
View File

@@ -282,7 +282,7 @@ static const struct i2c_device_id gsensor_mpu6500_id[] = {
static struct i2c_driver gsensor_mpu6500_driver = {
.probe = gsensor_mpu6500_probe,
.remove = gsensor_mpu6500_remove,
.remove = (void *)gsensor_mpu6500_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mpu6500_id,
.driver = {

2
drivers/input/sensors/accel/mpu6880_acc.c
View File

@@ -278,7 +278,7 @@ static const struct i2c_device_id gsensor_mpu6880_id[] = {
static struct i2c_driver gsensor_mpu6880_driver = {
.probe = gsensor_mpu6880_probe,
.remove = gsensor_mpu6880_remove,
.remove = (void *)gsensor_mpu6880_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mpu6880_id,
.driver = {

2
drivers/input/sensors/accel/mxc622x.c
View File

@@ -266,7 +266,7 @@ static const struct i2c_device_id gsensor_mxc6225_id[] = {
static struct i2c_driver gsensor_mxc6225_driver = {
.probe = gsensor_mxc6225_probe,
.remove = gsensor_mxc6225_remove,
.remove = (void *)gsensor_mxc6225_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mxc6225_id,
.driver = {

2
drivers/input/sensors/accel/mxc6655xa.c Executable file → Normal file
View File

@@ -244,7 +244,7 @@ static const struct i2c_device_id gsensor_mxc6655_id[] = {
static struct i2c_driver gsensor_mxc6655_driver = {
.probe = gsensor_mxc6655_probe,
.remove = gsensor_mxc6655_remove,
.remove = (void *)gsensor_mxc6655_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_mxc6655_id,
.driver = {

2
drivers/input/sensors/accel/sc7660.c
View File

@@ -1637,7 +1637,7 @@ static const struct i2c_device_id gsensor_sc7660_id[] = {
static struct i2c_driver gsensor_sc7660_driver = {
.probe = gsensor_sc7660_probe,
.remove = gsensor_sc7660_remove,
.remove = (void *)gsensor_sc7660_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_sc7660_id,
.driver = {

2
drivers/input/sensors/accel/sc7a20.c
View File

@@ -1750,7 +1750,7 @@ static const struct i2c_device_id gsensor_sc7a20_id[] = {
static struct i2c_driver gsensor_sc7a20_driver = {
.probe = gsensor_sc7a20_probe,
.remove = gsensor_sc7a20_remove,
.remove = (void *)gsensor_sc7a20_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_sc7a20_id,
.driver = {

2
drivers/input/sensors/accel/sc7a30.c
View File

@@ -1197,7 +1197,7 @@ static const struct i2c_device_id gsensor_sc7a30_id[] = {
static struct i2c_driver gsensor_sc7a30_driver = {
.probe = gsensor_sc7a30_probe,
.remove = gsensor_sc7a30_remove,
.remove = (void *)gsensor_sc7a30_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_sc7a30_id,
.driver = {

2
drivers/input/sensors/accel/stk8baxx.c
View File

@@ -938,7 +938,7 @@ static const struct i2c_device_id gsensor_stk8baxx_id[] = {
static struct i2c_driver gsensor_stk8baxx_driver = {
.probe = gsensor_stk8baxx_probe,
.remove = gsensor_stk8baxx_remove,
.remove = (void *)gsensor_stk8baxx_remove,
.shutdown = sensor_shutdown,
.id_table = gsensor_stk8baxx_id,
.driver = {

2
drivers/input/sensors/angle/angle_kxtik.c Executable file → Normal file
View File

@@ -380,7 +380,7 @@ static const struct i2c_device_id angle_kxtik_id[] = {
static struct i2c_driver angle_kxtik_driver = {
.probe = angle_kxtik_probe,
.remove = angle_kxtik_remove,
.remove = (void *)angle_kxtik_remove,
.shutdown = sensor_shutdown,
.id_table = angle_kxtik_id,
.driver = {

2
drivers/input/sensors/angle/angle_lis3dh.c Executable file → Normal file
View File

@@ -322,7 +322,7 @@ static const struct i2c_device_id angle_lis3dh_id[] = {
static struct i2c_driver angle_lis3dh_driver = {
.probe = angle_lis3dh_probe,
.remove = angle_lis3dh_remove,
.remove = (void *)angle_lis3dh_remove,
.shutdown = sensor_shutdown,
.id_table = angle_lis3dh_id,
.driver = {

2
drivers/input/sensors/compass/ak09911.c
View File

@@ -649,7 +649,7 @@ static const struct i2c_device_id compass_akm09911_id[] = {
static struct i2c_driver compass_akm09911_driver = {
.probe = compass_akm09911_probe,
.remove = compass_akm09911_remove,
.remove = (void *)compass_akm09911_remove,
.shutdown = sensor_shutdown,
.id_table = compass_akm09911_id,
.driver = {

2
drivers/input/sensors/compass/ak09918.c
View File

@@ -674,7 +674,7 @@ static const struct i2c_device_id compass_akm09918_id[] = {
static struct i2c_driver compass_akm09918_driver = {
.probe = compass_akm09918_probe,
.remove = compass_akm09918_remove,
.remove = (void *)compass_akm09918_remove,
.shutdown = sensor_shutdown,
.id_table = compass_akm09918_id,
.driver = {

2
drivers/input/sensors/compass/ak8963.c
View File

@@ -696,7 +696,7 @@ static const struct i2c_device_id compass_akm8963_id[] = {
static struct i2c_driver compass_akm8963_driver = {
.probe = compass_akm8963_probe,
.remove = compass_akm8963_remove,
.remove = (void *)compass_akm8963_remove,
.shutdown = sensor_shutdown,
.id_table = compass_akm8963_id,
.driver = {

2
drivers/input/sensors/compass/ak8975.c
View File

@@ -630,7 +630,7 @@ static const struct i2c_device_id compass_akm8975_id[] = {
static struct i2c_driver compass_akm8975_driver = {
.probe = compass_akm8975_probe,
.remove = compass_akm8975_remove,
.remove = (void *)compass_akm8975_remove,
.shutdown = sensor_shutdown,
.id_table = compass_akm8975_id,
.driver = {

2
drivers/input/sensors/gyro/ewtsa.c
View File

@@ -443,7 +443,7 @@ static const struct i2c_device_id gyro_ewtsa_id[] = {
static struct i2c_driver gyro_ewtsa_driver = {
.probe = gyro_ewtsa_probe,
.remove = gyro_ewtsa_remove,
.remove = (void *)gyro_ewtsa_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_ewtsa_id,
.driver = {

2
drivers/input/sensors/gyro/iam20680_gyro.c
View File

@@ -176,7 +176,7 @@ static const struct i2c_device_id gyro_iam20680_id[] = {
static struct i2c_driver gyro_iam20680_driver = {
.probe = gyro_iam20680_probe,
.remove = gyro_iam20680_remove,
.remove = (void *)gyro_iam20680_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_iam20680_id,
.driver = {

2
drivers/input/sensors/gyro/icm2060x_gyro.c
View File

@@ -186,7 +186,7 @@ static const struct i2c_device_id gyro_icm2060x_id[] = {
static struct i2c_driver gyro_icm2060x_driver = {
.probe = gyro_icm2060x_probe,
.remove = gyro_icm2060x_remove,
.remove = (void *)gyro_icm2060x_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_icm2060x_id,
.driver = {

2
drivers/input/sensors/gyro/icm4260x_gyro.c
View File

@@ -182,7 +182,7 @@ static const struct i2c_device_id gyro_icm4260x_id[] = {
static struct i2c_driver gyro_icm4260x_driver = {
.probe = gyro_icm4260x_probe,
.remove = gyro_icm4260x_remove,
.remove = (void *)gyro_icm4260x_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_icm4260x_id,
.driver = {

2
drivers/input/sensors/gyro/l3g20d.c
View File

@@ -239,7 +239,7 @@ static const struct i2c_device_id gyro_l3g20d_id[] = {
static struct i2c_driver gyro_l3g20d_driver = {
.probe = gyro_l3g20d_probe,
.remove = gyro_l3g20d_remove,
.remove = (void *)gyro_l3g20d_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_l3g20d_id,
.driver = {

2
drivers/input/sensors/gyro/l3g4200d.c
View File

@@ -239,7 +239,7 @@ static const struct i2c_device_id gyro_l3g4200d_id[] = {
static struct i2c_driver gyro_l3g4200d_driver = {
.probe = gyro_l3g4200d_probe,
.remove = gyro_l3g4200d_remove,
.remove = (void *)gyro_l3g4200d_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_l3g4200d_id,
.driver = {

2
drivers/input/sensors/gyro/lsm330_gyro.c
View File

@@ -244,7 +244,7 @@ static const struct i2c_device_id gyro_lsm330_id[] = {
static struct i2c_driver gyro_lsm330_driver = {
.probe = gyro_lsm330_probe,
.remove = gyro_lsm330_remove,
.remove = (void *)gyro_lsm330_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_lsm330_id,
.driver = {

2
drivers/input/sensors/gyro/mpu6500_gyro.c
View File

@@ -186,7 +186,7 @@ static const struct i2c_device_id gyro_mpu6500_id[] = {
static struct i2c_driver gyro_mpu6500_driver = {
.probe = gyro_mpu6500_probe,
.remove = gyro_mpu6500_remove,
.remove = (void *)gyro_mpu6500_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_mpu6500_id,
.driver = {

2
drivers/input/sensors/gyro/mpu6880_gyro.c
View File

@@ -186,7 +186,7 @@ static const struct i2c_device_id gyro_mpu6880_id[] = {
static struct i2c_driver gyro_mpu6880_driver = {
.probe = gyro_mpu6880_probe,
.remove = gyro_mpu6880_remove,
.remove = (void *)gyro_mpu6880_remove,
.shutdown = sensor_shutdown,
.id_table = gyro_mpu6880_id,
.driver = {

2
drivers/input/sensors/hall/och165t_hall.c
View File

@@ -141,7 +141,7 @@ static const struct i2c_device_id hall_och165t_id[] = {
static struct i2c_driver hall_och165t_driver = {
.probe = hall_och165t_probe,
.remove = hall_och165t_remove,
.remove = (void *)hall_och165t_remove,
.shutdown = sensor_shutdown,
.id_table = hall_och165t_id,
.driver = {

2
drivers/input/sensors/lsensor/cm3217.c Executable file → Normal file
View File

@@ -220,7 +220,7 @@ static const struct i2c_device_id light_cm3217_id[] = {
static struct i2c_driver light_cm3217_driver = {
.probe = light_cm3217_probe,
.remove = light_cm3217_remove,
.remove = (void *)light_cm3217_remove,
.shutdown = sensor_shutdown,
.id_table = light_cm3217_id,
.driver = {

2
drivers/input/sensors/lsensor/cm3218.c
View File

@@ -397,7 +397,7 @@ static const struct i2c_device_id light_cm3218_id[] = {
static struct i2c_driver light_cm3218_driver = {
.probe = light_cm3218_probe,
.remove = light_cm3218_remove,
.remove = (void *)light_cm3218_remove,
.shutdown = sensor_shutdown,
.id_table = light_cm3218_id,
.driver = {

2
drivers/input/sensors/lsensor/cm3232.c Executable file → Normal file
View File

@@ -227,7 +227,7 @@ static const struct i2c_device_id light_cm3232_id[] = {
static struct i2c_driver light_cm3232_driver = {
.probe = light_cm3232_probe,
.remove = light_cm3232_remove,
.remove = (void *)light_cm3232_remove,
.shutdown = sensor_shutdown,
.id_table = light_cm3232_id,
.driver = {

2
drivers/input/sensors/lsensor/isl29023.c Executable file → Normal file
View File

@@ -255,7 +255,7 @@ static const struct i2c_device_id light_isl29023_id[] = {
static struct i2c_driver light_isl29023_driver = {
.probe = light_isl29023_probe,
.remove = light_isl29023_remove,
.remove = (void *)light_isl29023_remove,
.shutdown = sensor_shutdown,
.id_table = light_isl29023_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_al3006.c Executable file → Normal file
View File

@@ -282,7 +282,7 @@ static const struct i2c_device_id light_al3006_id[] = {
static struct i2c_driver light_al3006_driver = {
.probe = light_al3006_probe,
.remove = light_al3006_remove,
.remove = (void *)light_al3006_remove,
.shutdown = sensor_shutdown,
.id_table = light_al3006_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_ap321xx.c
View File

@@ -395,7 +395,7 @@ static const struct i2c_device_id light_ap321xx_id[] = {
static struct i2c_driver light_ap321xx_driver = {
.probe = light_ap321xx_probe,
.remove = light_ap321xx_remove,
.remove = (void *)light_ap321xx_remove,
.shutdown = sensor_shutdown,
.id_table = light_ap321xx_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_em3071x.c
View File

@@ -265,7 +265,7 @@ static const struct i2c_device_id light_em3071x_id[] = {
static struct i2c_driver light_em3071x_driver = {
.probe = light_em3071x_probe,
.remove = light_em3071x_remove,
.remove = (void *)light_em3071x_remove,
.shutdown = sensor_shutdown,
.id_table = light_em3071x_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_stk3171.c Executable file → Normal file
View File

@@ -301,7 +301,7 @@ static const struct i2c_device_id light_stk3171_id[] = {
static struct i2c_driver light_stk3171_driver = {
.probe = light_stk3171_probe,
.remove = light_stk3171_remove,
.remove = (void *)light_stk3171_remove,
.shutdown = sensor_shutdown,
.id_table = light_stk3171_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_stk3332.c
View File

@@ -354,7 +354,7 @@ static const struct i2c_device_id light_stk3332_id[] = {
static struct i2c_driver light_stk3332_driver = {
.probe = light_stk3332_probe,
.remove = light_stk3332_remove,
.remove = (void *)light_stk3332_remove,
.shutdown = sensor_shutdown,
.id_table = light_stk3332_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_stk3410.c
View File

@@ -356,7 +356,7 @@ static const struct i2c_device_id light_stk3410_id[] = {
static struct i2c_driver light_stk3410_driver = {
.probe = light_stk3410_probe,
.remove = light_stk3410_remove,
.remove = (void *)light_stk3410_remove,
.shutdown = sensor_shutdown,
.id_table = light_stk3410_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_ucs14620.c
View File

@@ -344,7 +344,7 @@ static const struct i2c_device_id light_ucs14620_id[] = {
static struct i2c_driver light_ucs14620_driver = {
.probe = light_ucs14620_probe,
.remove = light_ucs14620_remove,
.remove = (void *)light_ucs14620_remove,
.shutdown = sensor_shutdown,
.id_table = light_ucs14620_id,
.driver = {

2
drivers/input/sensors/lsensor/ls_us5152.c
View File

@@ -420,7 +420,7 @@ static const struct i2c_device_id light_us5152_id[] = {
static struct i2c_driver light_us5152_driver = {
.probe = light_us5152_probe,
.remove = light_us5152_remove,
.remove = (void *)light_us5152_remove,
.shutdown = sensor_shutdown,
.id_table = light_us5152_id,
.driver = {

2
drivers/input/sensors/pressure/pr_ms5607.c Executable file → Normal file
View File

@@ -279,7 +279,7 @@ static const struct i2c_device_id pressure_ms5607_id[] = {
static struct i2c_driver pressure_ms5607_driver = {
.probe = pressure_ms5607_probe,
.remove = pressure_ms5607_remove,
.remove = (void *)pressure_ms5607_remove,
.shutdown = sensor_shutdown,
.id_table = pressure_ms5607_id,
.driver = {

2
drivers/input/sensors/psensor/ps_al3006.c Executable file → Normal file
View File

@@ -243,7 +243,7 @@ static const struct i2c_device_id proximity_al3006_id[] = {
static struct i2c_driver proximity_al3006_driver = {
.probe = proximity_al3006_probe,
.remove = proximity_al3006_remove,
.remove = (void *)proximity_al3006_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_al3006_id,
.driver = {

2
drivers/input/sensors/psensor/ps_ap321xx.c
View File

@@ -307,7 +307,7 @@ static const struct i2c_device_id proximity_ap321xx_id[] = {
static struct i2c_driver proximity_ap321xx_driver = {
.probe = proximity_ap321xx_probe,
.remove = proximity_ap321xx_remove,
.remove = (void *)proximity_ap321xx_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_ap321xx_id,
.driver = {

2
drivers/input/sensors/psensor/ps_em3071x.c
View File

@@ -262,7 +262,7 @@ static const struct i2c_device_id proximity_em3071x_id[] = {
static struct i2c_driver proximity_em3071x_driver = {
.probe = proximity_em3071x_probe,
.remove = proximity_em3071x_remove,
.remove = (void *)proximity_em3071x_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_em3071x_id,
.driver = {

2
drivers/input/sensors/psensor/ps_stk3171.c Executable file → Normal file
View File

@@ -250,7 +250,7 @@ static const struct i2c_device_id proximity_stk3171_id[] = {
static struct i2c_driver proximity_stk3171_driver = {
.probe = proximity_stk3171_probe,
.remove = proximity_stk3171_remove,
.remove = (void *)proximity_stk3171_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_stk3171_id,
.driver = {

2
drivers/input/sensors/psensor/ps_stk3332.c
View File

@@ -365,7 +365,7 @@ static const struct i2c_device_id proximity_stk3332_id[] = {
static struct i2c_driver proximity_stk3332_driver = {
.probe = proximity_stk3332_probe,
.remove = proximity_stk3332_remove,
.remove = (void *)proximity_stk3332_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_stk3332_id,
.driver = {

2
drivers/input/sensors/psensor/ps_stk3410.c
View File

@@ -359,7 +359,7 @@ static const struct i2c_device_id proximity_stk3410_id[] = {
static struct i2c_driver proximity_stk3410_driver = {
.probe = proximity_stk3410_probe,
.remove = proximity_stk3410_remove,
.remove = (void *)proximity_stk3410_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_stk3410_id,
.driver = {

2
drivers/input/sensors/psensor/ps_ucs14620.c
View File

@@ -343,7 +343,7 @@ static const struct i2c_device_id proximity_ucs14620_id[] = {
static struct i2c_driver proximity_ucs14620_driver = {
.probe = proximity_ucs14620_probe,
.remove = proximity_ucs14620_remove,
.remove = (void *)proximity_ucs14620_remove,
.shutdown = sensor_shutdown,
.id_table = proximity_ucs14620_id,
.driver = {

0
drivers/input/sensors/sensor-i2c.c Executable file → Normal file
View File

2
drivers/input/sensors/temperature/tmp_ms5607.c Executable file → Normal file
View File

@@ -296,7 +296,7 @@ static const struct i2c_device_id temperature_ms5607_id[] = {
static struct i2c_driver temperature_ms5607_driver = {
.probe = temperature_ms5607_probe,
.remove = temperature_ms5607_remove,
.remove = (void *)temperature_ms5607_remove,
.shutdown = sensor_shutdown,
.id_table = temperature_ms5607_id,
.driver = {

Some files were not shown because too many files have changed in this diff Show More