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PD#156734: emmc: refixed core phase value for emmc highspeed busmode

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Change-Id: I33ce650b3ed9dd6eac41b0814679fb660991a738
Signed-off-by: Long Yu <long.yu@amlogic.com>
This commit is contained in:
Long Yu
2018-02-07 17:47:08 +08:00
committed by Jianxin Pan
parent 2a59abcbba
commit fc3de90be4
1 changed files with 6 additions and 4 deletions
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10
drivers/amlogic/mmc/aml_sd_emmc_v3.c
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@@ -241,10 +241,12 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_host *host,
clkc->core_phase = 2;
pr_info("%s: try set sd/emmc to DDR mode\n",
mmc_hostname(host->mmc));
} else if ((timing == MMC_TIMING_MMC_HS)
&& (host->data->chip_type < MMC_CHIP_G12A))
clkc->core_phase = 3;
else if ((timing == MMC_TIMING_MMC_HS200)
} else if (timing == MMC_TIMING_MMC_HS) {
if (host->data->chip_type < MMC_CHIP_G12A)
clkc->core_phase = 3;
else
clkc->core_phase = 2;
} else if ((timing == MMC_TIMING_MMC_HS200)
|| ((timing == MMC_TIMING_SD_HS)
&& aml_card_type_non_sdio(pdata))
|| (timing == MMC_TIMING_UHS_SDR104)) {