shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 10:31:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: get the real dclk parent

Browse Source 
When assign the vp dclk parent as hdmi phy pll in dts. The
vp dclk parent should get by clk_get_parent. The vp.dclk_parent
is not the real parent.

Change-Id: I4b1ba1e1b46e2f5db323069402c4b322ba4a836f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This commit is contained in:
Zhang Yubing
2024-08-12 14:15:39 +08:00
committed by 张玉炳
parent f9e84f307a
commit fc8a056676
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -8498,8 +8498,8 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
request_clock = request_clock >> 2;
}
clock = rockchip_drm_dclk_round_rate(vop2->version,
vp->dclk_parent ? vp->dclk_parent : vp->dclk,
request_clock * 1000) / 1000;
vp->dclk_parent ? clk_get_parent(vp->dclk) :
vp->dclk, request_clock * 1000) / 1000;
}
/*
@@ -8925,8 +8925,8 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
adj_mode->crtc_clock =
rockchip_drm_dclk_round_rate(vop2->version,
vp->dclk_parent ? vp->dclk_parent : vp->dclk,
adj_mode->crtc_clock * 1000);
vp->dclk_parent ? clk_get_parent(vp->dclk) :
vp->dclk, adj_mode->crtc_clock * 1000);
adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000);
}
return true;