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clk: rockchip: rk3288: Add 420MHz for PLL

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Change-Id: Ic722bdf5d467a64cdf093f8bdabb6dab533cd230
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2019-03-28 14:37:04 +08:00
committed by Tao Huang
parent 6b1d3f74d8
commit ff106652d9
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3288.c
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@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 500000000, 3, 125, 2),
RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 420000000, 1, 70, 4),
RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 400000000, 3, 100, 2),
RK3066_PLL_RATE( 384000000, 2, 128, 4),