The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 95e0c473a0ac1bdac25f55678dc602eb50dae684)
Change-Id: I77872b5fb33eb92402e9036b97b185ea56eb45c6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 86609a6613c64ee9272da1fd2f578d4beab2174e)
Conflicts:
drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, and apply this patch for
clk-rk3366 manually.]
Change-Id: I2d73c90eb6f43150725c81417af37a6a562cd329
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit a96edf5a5243e1bdf642492b783221aa498f1e49)
Change-Id: I9a51ed269fe26742da2ae84d99cf9689f49add1b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null
drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
* struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
* struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
* struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 1c908b320055e1ce706e91121dbb2ce7934c788f)
Change-Id: I18dbd45ebd528fe2a871c98a1561dd0c0bf41e13
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.
Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864)
Conflicts:
drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3228.c
drivers/clk/rockchip/clk-rk3366.c
[zx: keep calling clk_register_fixed_factor previouslly, and there
is no rk3228 clock controller, add support for clk-rk3366 manually,
because it is not in the upstream codes.]
Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
commit 0fda2be634398f4b8d53c0436311f99557e56c4e)
Conflicts:
drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply this patch for
clk-rk3366.]
Change-Id: I48fde9facccd41585873c997b0b02a7a73972717
As commit 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.
The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.
Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.
This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.
For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.
With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.
Fixes: 1d33929e2a ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit dfff24bde7)
Conflicts:
drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply for clk-rk3366]
Change-Id: I2e91afd893c87eb3ab8a41db1fe81f5c43409951
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 1d33929e2a)
Change-Id: Ic01f80e6f33ae84cc87e954aae35f26b6f1a5434
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
For InnoSilicon usb2.0 phy, there is no siddq bit for operating,
what is more, when we control usb phy to suspend, its Plls will
not be affected. So we can operate resume/suspend bits directly
when it is going to power on/off.
Change-Id: I6bfe6b1a90b1bdcb0b0d5b670d579a625b22c0ba
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Compatible "rockchip,rk336x-usb-phy" support to RK3368 & RK3366.
Change-Id: I435ecd0a9f1c2a50836f7e3c44b6089ba49d728a
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Because there are some frac clock mux nodes don't have a gate node on
the RK3399.
Change-Id: I4791b90a08faab286743a5cba30738cfb046594c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
commit ffd9d4d39ef7ff90364d3abd6c39919e6582b605)
Set the newly added id for mpll_src and 32k, so that they can be called
in other parts.
Change-Id: Ief82231215a147b62abcfbb5565054470fc9ea37
Signed-off-by: Feng Xiao <xf@rock-chips.com>
This patch enables the tsadc for rk3399 evb board.
The rk3399 evb board uses the gpio to reset the chip since it connects the
PMIC to work, and TSHUT is low active on evb board.
Change-Id: Ibd4fc2c752fe1f34cc231385ee314e4b9a32e970
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch adds the thermal needed main information for rk3399 SoCS.
Basically has the following content:
1) TSADC controller:
Add the needed attributes for rk3399 TSADC controller.
Especially for the TSHUT, in some cases if we are unable to shut it down
in orderly fashion (says: kernel is stuck holding a lock or similar), then
hardware TSHUT will reset it.
If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.
2) Thermal zones:
Add the needed device mode for thermal generic framework.
Detail in Documentation/devicetree/bindings/thermal/thermal.txt.
Change-Id: I1361beeb85e6d4a134b4640c16440452aa950e16
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
According to a description from TRM, add all the power domains
Change-Id: Ibbf17fb1edc125358760db8acd99dd681913cd3c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Get the gamma value from screen vendor and use the following
algorithm to get the cabc lut
for(i=0;i<256;i++)
cabc_lut[i] = pow((256.0/(i + 256)), gamma_val) * 65536 + 0.5;
Change-Id: I8500cc84869d2693ce6af4e116b2140b3d3a16fc
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
Rockchip_spi_set_cs could be called by spi_setup, but
spi_setup may be called by device driver after runtime suspend.
Then the spi clock is closed, rockchip_spi_set_cs may access the
spi registers, which causes cpu block in some socs.
Change-Id: I58915aee30cfbd3098eb137e3d9046b59ad9476c
Fixes: 64e36824b3 ("spi/rockchip: add driver for Rockchip RK3xxx")
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/spi.git for-next
commit b920cc3191)
Add devicetree bindings for Rockchip rk3399 spi which found on
Rockchip rk3399 SoCs.
Change-Id: Ib43ec4ce8970359f660311fce35017843f8998df
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/spi.git for-next
commit 9b7a562215)
This patchset add the thermal for RK3368 dts,
Since the two CPU clusters, with four CPU core for each cluster,
one cluster is optimized for high-performance(big cluster) and the othe
is optimized for low power(little cluster).
This patch adds the second order for thermal throttle, and the critical
temperature for thermal over-tempeature protection on Software.
Change-Id: I9491287695768530c557511097f79ad6188adf1b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c68bb56efb)
rk3366 timing reg config change to frame effect,
so we need config done after update timing.
Change-Id: I7279fc03a066357cb8a0ed452e9182f92bf90f01
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
like rk3366 vop0 is different from vop1, so fb[rk_fb->num_fb >> 1]
is not correct for extend vop fb info.
Change-Id: Ie7ed0614a5cb32fcb22707c88aa70be45cb243d7
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
There is a div2 behind wifi pll, so the initial rate should be 960MHz.
Change-Id: Ib90457a0b17907c3056adf58edd623ae462b06a3
Signed-off-by: Feng Xiao <xf@rock-chips.com>
