To use tsadc_shut_m0 function, tsadc must switch to cru_shut_mode,
because tsadc_shut signal have to go through the cru to get to tsadc_shut_m0 signal.
Refer to "10.10.10.81\技术文档\thermal\rk3568_tsadc_shut.png" for details.
Change-Id: I0528917efe2f5ea6f002ebf1608815eb01f552c0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
This is for mipi dsi on rk356x: there
is a hold signal from mipi dsi to
vop.
Mipi dsi may trigger the hold signal
when send dsi command or switch between
video mode and command mode.
vop may run into an unexpected situation if this hold
signal is rise when vop is running.
So when mipi dsi switch between video mode
or command mode, or send a dsi command, it
should set vop in stanby state.
Change-Id: I80e456d3416518436045ae8e0eec215c22b111a3
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The f_uac1 use ep address 0x81 and 0x01 for set sample rate,
so it can only support uac1 ep1-in and ep1-out to set playback
and capture sample rate, it has limitation for USB composite
device (e.g. RNDIS & UAC1). This patch use in_ep->address and
out_ep->address instead of the fixed addresses.
Change-Id: Ie2c70e2c2ec89fb66b00cd2a64928b50ee0541cc
Signed-off-by: William Wu <william.wu@rock-chips.com>
Rechange the emmc aliase to mmc2 to be same as other rockchip's chips,
so the android application can process the emmc property of all chips
in a uniform manner.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Ia092ec08552e360e7fc5dc271dbb69edc08bd486
Rechange the emmc aliases to mmc2 to be same as other rockchip's chips,
so the android application can process the emmc property of all chips
in a uniform manner.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Id1bbd8c63f919eb13cd7b511e9afe885753d99f5
Solve the problem of insufficient power supply voltage of
USB peripheral
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: I7e06b463a2da567fcf8fa2fc641379d9274ed549
The drm core will disable than enable a crtc when is marked as
connectors_changed.
But when we attach a writeback connector to a running
crtc, we really don't need this disable/enable, which
will black a running screen.
Change-Id: I636615f27424bc60496ffc487c218f60fb95d719
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
According test, if sensor output 2mux mode, cif needs to be
configured BT656_1120_MULTI_ID_MODE_2, nor no interrupts will be
triggered. So BT656_1120_MULTI_ID_MODE_2 & BT656_1120_MULTI_ID_MODE_4
is different, distinguish it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I8e1959131708d2cab87ab086e03023a718f5b807
the poweroff work contains an operation to release the gpu
wake_lock, sometimes, the deferrable work can cause the gpu
wake_lock to be delayed for tens of seconds before release,
the device can not into deepsleep, resulting in increased
power consumption.
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I49aba25cfc000739f344420f818c91b382926e6e
Donot pull up BT uart pin before rtl87xx power on.
Signed-off-by: Longjian Lin <llj@rock-chips.com>
Change-Id: I562e4c403f2a56f9253ff677d78d9056cd98a54d
As per UAC1.0 spec Table 4-2: Class-Specific AC Interface
Header Descriptor, the baInterfaceNr(n) are indicated the
interface number of each AudioStreaming. So it needs to
set the baInterfaceNr dynamically according to the interface
IDs allocated by the usb gadget core.
Change-Id: I57cc7b0070fb166aac4360262b2a7e6f2f5df6e1
Signed-off-by: William Wu <william.wu@rock-chips.com>
When system reboot, drm framework will set mode to
prefer mode first then set mode to 0. Clearing flag
in encoder enable will causes the VOP to not set
the sync polarity.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I20dfcc7b6dc76faf903b42620454a7f5071bd3e3
For resolution floating refresh rate such as 59.94 Hz,
the only difference between the resolution and its
corresponding integer refresh rate resolution is the clock.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I149471f58c9eb65f972139b23a45339ea8807e54
1. Add mpp_dev task capacity and default is 1.
The task capacity is the task queue length that hardware can accept.
Default 1 means normal hardware can only accept one task at once.
2. Attach mpp_dev to mpp_taskqueue for status probe. The task queue
capacity is the minimum task capacity of all the attached mpp_dev.
Change-Id: I8cafe806ec9399902237418d2bbcb088240ed415
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
There are some clks(uart) that do not have to comply with the 20 times
fractional divider limit.
Change-Id: I420d8ba3b5de65d9e0ea74920d5ea8450ae94465
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK356X DWC3 supports to set the USB 2.0 PHY enter
suspend mode if the DWC3 core suspend conditions are
valid (as per DWC3 controller databook 6.3.46 GUSB2PHYCFG
register bit6). This cause xHC driver failed to send
USB resume signal to USB 2.0 device in xhci_bus_resume().
This patch adds a quirk "xhci-u2-broken-suspend" to force
the xHC to set the link state to XDEV_RESUME and send USB
resume signal to USB 2.0 device.
Change-Id: I24c017867f80728890c0562a12e4554625913e67
Signed-off-by: William Wu <william.wu@rock-chips.com>
Rockchip SNPS xHC 3.0 set USB 2.0 PHY enter suspend mode
from DWC3 core if the suspend conditions are valid (as per
DWC3 controller databook 6.3.46 GUSB2PHYCFG register bit6).
In this case, it needs to set the bus_suspended bit for
USB 2.0, so that in xhci_bus_resume, it can set the xHC
link state to XDEV_RESUME and send USB resume signal to
USB 2.0 device.
Test on RK3568 USB 3.0 Host interface with USB 2.0 Camera
or USB 2.0 HUB which support USB auto suspend. Without this
patch, the xHC fails to send USB resume signal on the USB
bus to wakeup the USB 2.0 devices, and cause xHC died.
Change-Id: Icb5a553d71a5f3144d77f8d5a5132892a5795285
Signed-off-by: William Wu <william.wu@rock-chips.com>
The DWC3 suspend event is used for special usb gadgets
which support usb auto suspend, such as UVC. So disable
the suspend event by default, and enable it depends on
the uwk_en flag. This can avoid printing redundant log
continuously in some case like this:
[47.526109] dwc3 fcc00000.dwc3: device suspend
[47.527118] dwc3 fcc00000.dwc3: device suspend
[47.528200] dwc3 fcc00000.dwc3: device suspend
[47.529110] dwc3 fcc00000.dwc3: device suspend
[47.530120] dwc3 fcc00000.dwc3: device suspend
Change-Id: I1945eba68d4bb1639d9c3ace66a8caea023371cc
Signed-off-by: William Wu <william.wu@rock-chips.com>
On Rockchip platforms, we use TRB_ENT for bulk Tx TRB.
However, the TRB_ENT can only be enabled for TRB if
the transfer length of the TRB is an integer multiple
of the EP maxpacket. The current code only check the
transfer length of the first TRB, it's not enough.
Without this patch, the xHCI fail to do Read(10) command
with the U3 Disk used VFAT filesystem on RK3566 Box board
(2 + 4)G DDR, the error log like this:
[ 23.165539] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 23.183342] usb 2-1: New USB device found, idVendor=0781, idProduct=55a3, bcdDevice= 1.00
[ 23.183418] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 23.183434] usb 2-1: Product: Ultra Luxe
[ 23.183447] usb 2-1: Manufacturer: SanDisk
...
[ 23.186615] usb-storage 2-1:1.0: USB Mass Storage device detected
[ 23.189013] scsi host0: usb-storage 2-1:1.0
[ 24.217186] scsi 0:0:0:0: Direct-Access SanDisk Ultra Luxe 1.00 PQ: 0 ANSI: 6
[ 24.219712] sd 0:0:0:0: [sda] 120127488 512-byte logical blocks: (61.5 GB/57.3 GiB)
[ 24.221263] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 24.221301] sd 0:0:0:0: [sda] Write Protect is off
[ 24.222162] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 24.243346] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 24.642325] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 25.862084] usb 2-1: reset SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 25.882974] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK
[ 25.883003] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 00 50 28 01 00 00 3f 00
[ 28.349195] usb 2-1: reset SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 28.366763] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK
[ 28.366823] sd 0:0:0:0: [sda] tag#0 CDB: Read(10) 28 00 01 15 4b 81 00 00 3f 00
Fixes: 0f580acb01 ("usb: xhci: add support for xhci trb ent quirk")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iaa8f87eba3146c09fda858704c96644da40f5859
If hdmi mode is changed but not plug out, encoder disabled
is after encoder atomic check, hdmi output_if won't be set
when crtc atomic enable, sync polarity won't be set correctly.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I2e3244c4f8f9f9fd565170d50f39710749085b98
rk3568 CIF_REG_GRF_CIFIO_CON1 reg has been omitted, fix it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ib489312ae129fd522c7d23f55d14a7852086df25
