enable too early may lead to mipi csi2 overflow
Change-Id: Ib4d1f59803b8dcfdea8ba219fe8dc9667db35428
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Avoid commit new plane time close to vsync at async mode, the following
case maybe lead to error:
vsync[1]->update plane[2]->config done[3]->update plane[4]->vsync[5]
If new vsync[5] insert step 4, only part of plane register complete,
this will lead to part of plane register take effect and lead to error.
So we introduce this safeguard, when commit time exceeds 15/16 of a
frame, this frame will be postponed to the next frame.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4e405baf6ac080f6990e94f639c168ff9f0daf1c
The vop2_win_disable() may be called multiple times in a short period
before the fs comes. Using VOP_WIN_GET(vop2, win, enable) for
judgment may cause double disable of win, leading to double decrement
of vop2_power_domain.ref_count.
This patch uses regbak to determine whether win is already disabled
in vop2_win_disable(), similar to what is done in the
vop2_win_enable().
Change-Id: I3095ef0ef0068ef3dd7245375127083a17871341
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
If the power domain has a parent power domain, the ref_count of
parent power domain should also be set during initialization.
Change-Id: I4948d11fee2829049559541040ae2117ca319329
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
If the PD has already been turned off, and the value of
vop2_power_domain.ref_count is zero at this time, calling
vop2_power_domain_put() again will cause ref_count to underflow.
This underflow will be interpreted as if the PD has been turned on.
Fixes: aa3aee14d0 ("drm/rockchip: vop2: Add vop2 internal pd support for rk3588")
Change-Id: Ia814c5907072cd1aee785734e36053cba7382b23
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
When do 'echo 1 > /proc/sys/abi/swp' on two cpus at the same time, we can see:
call_undef_hook() at traps.c:442
do_undefinstr() at traps.c:504
el0_undef() at entry-common.c:605
el0t_64_sync_handler() at entry-common.c:689
el0t_64_sync() at entry.S:585
That is because write swp 1 at the same time, add the swp_hooks to the undef_hook
list twice, swp_hooks list node's next becomes itself. When list_for_each_entry of
the undef_hook, cpu loops forever here.
Change-Id: Ice60dbc633020220e7218a554e9d0e4c7dacceb4
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Previously, Valhall and Bifrost GPUs shared a single driver source directory (drivers/gpu/arm/bifrost).
However, starting from DDK r52 (g27), Bifrost GPUs are no longer supported.
As a result, the Valhall GPU driver from DDK r53 (g28) must use a separate source directory
(drivers/gpu/arm/valhall).
There are also modifications in some header files outside of drivers/gpu/arm/.
In addition, the configs related to Bifrost and Valhall GPUs have been removed
from the defconfig file like rockchip_linux_defconfig,
which does not reflect the current SoC.
Instead, these configs have been migrated to the .config files
such as rk3576.config, whose file names can reflect the current SoC.
Therefore, for some SoCs, the kernel compilation command line needs to be adjusted.
Change-Id: I0c4384212b4b679a728401f7f89ae839530f002b
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
DSI works in command mode, using long packet DCS commands WMC and WMS
to send video signals at high speed.
Change-Id: Ib95e9e2228d6393f85f7d3e53918d538f34d9b72
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
If the CONSOLE_LOGLEVEL_DEFAULT is over 6, there should be the
related log:
......
[ 69.489746][ T300] rockchip-dp 27dc0000.edp: Enter panel self test mode
......
Change-Id: I256933ef2cff20716715c5850948a85e4c8fad07
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The LCH should always be accessed under lock protection to avoid
race conditions that could lead to null-pointer dereference.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I26ef5467c4d79236e1d52806fec7d60c0c34136f
The transferred bytes are calculated by subtracting first_lli.base from
current position (cur_pos). However, cur_pos remains 0 until the first
burst transfer completes, which could result in a negative value.
This leads to incorrect byte count reporting.
Fix the overflow by clamping the calculated bytes to 0 when negative,
ensuring the reported transfer position matches hardware state before
the first burst completion.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie9d14f514d2ebfe068b535b2f9892b319cb8a41b
When all layers are rgb, the post-csc input color encoding
is fixed to rgb full, and the value of input_color_encoding
has no actual utility. If there are any yuv planes, value
of post-csc input_color_encoding selects the value of the
yuv plane with the largest area.
Change-Id: If624730e93a5ac03fc334890074883b9e6b828eb
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
For wave mode, the duty and period share memory to update, so it is
sufficient to config &rockchip_pwm_wave_config.wave_table and set
&rockchip_pwm_wave_config.duty_*/&rockchip_pwm_wave_config.period_*
for the update of duty and period.
Change-Id: Ide133377991a9a6c2c26c4de4cb91040f6a7eadd
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Also, the setting of rk_dsm_set_clk() is only in the playback stream.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I142091151f94cc62b4b22f4079d3ab03f9dce57f
When dci is not enabled and vp is yuv overlay, the input
range of csc is limited.
Fixes: c08d820f80 ("drm/rockchip: vop2: Support post csc color range convert")
Change-Id: I53064bcbb46f8d2fda70eb71577e79ea32399690
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
