The clock frequency should be between 500KHz and 800KHz, 650KHz is
a typical value.
Change-Id: I8ee3d1e0204c6580d508029e6212e232527c644a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This patch delete the mutex in dw_hdmi_suspend. For there is no
need to use mutex to protect disable_irq. And the same mutex is
also used in the dw_hdmi_irq, mutex deadlock will occur when
dw_hdmi_suspend and dw_hdmi_irq are called at the same time.
Change-Id: I8cb6a6483aa4d32882e814656dd93317b5da9ad3
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This driver supports MIPI RX DPHY with Synopsys or Innosilicon IP block.
It is also a v4l2 subdev driver.
Also select PHY_ROCKCHIP_MIPI_RX when VIDEO_ROCKCHIP_ISP1 or
VIDEO_ROCKCHIP_CIF is enabled.
Change-Id: I6d828c9e506f03d4a530d80ab8419f5cddeff7d7
Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
If encoder does not support HDR, the DRM_ERROR print in
hdmi_config_hdr_infoframe would be misleading to there is
abnormal error in drm/hdmi. Now change it to DRM_DEBUG.
Change-Id: Icdaa4ea408542c6428e22948522ed2017475ea18
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If lane_rate is bigger than 1Gbps, the UI is less than
1 ns, so we use ps as the basic units.
Change-Id: I00c1dd17a017d87a795ce6f70213de1adf50d5e2
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
As clock frequency should be between 500KHz and 800KHz, inter_pd_soc
should be no less than 90us and bandgap chopper function should be
enabled, add a new initialize function to handle the power sequence
for rk1808 SoCs.
Change-Id: Ia1ad81783ccc34bc4218dbbd62f7710ee0773b0a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
SoC data initialization requires the use of regmap base,
but it is no initialized at this time, and regmap base needs
to use ctrl data, so splitting it into two functions.
Fixes: f82750e615 ("pinctrl: rockchip: Call rockchip_pinctrl_get_soc_data() after regmap Initialization")
Change-Id: Ife46a9ade41f021458336c3480cdf99a96c2f264
Signed-off-by: David Wu <david.wu@rock-chips.com>
add descriptions for these control definitions.
Change-Id: I212729e9ecba211c7e57f73cd5f437620284d1e9
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This allows 32 bit owners of uvc video to make ioctls
into a 64 bit kernel.
All of the current uvc ioctls can be handled with the
same struct definitions as regular ioctl.
Change-Id: Ia31b26147ab619f0673f94b6662eaf181a9eb5dd
Signed-off-by: William Wu <william.wu@rock-chips.com>
The clock frequency should be between 500KHz and 800KHz, 650KHz is
a typical value.
Change-Id: Id8a81f667350747576f803ce5259b4e09076be89
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Innosilicon combophy for PCIe still need different
configuration between EP and RC mode.
Change-Id: I48fb3f7bc2b73cba1adc4ba026b751dbe227a30f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Innosilicon combophy for PCIe still need different
configuration between EP and RC mode.
Change-Id: Ie1f14e63785f44d84a2b3a154990c6a54eb1156e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The original combo phy driver can't work properly for PCIe.
Fix it.
Change-Id: I68ddabe5aa9592d7d36b8b0f0050a0d9bd843f44
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Innosilicon combphy need release link reset grant
when finishing PLL lock, so we need the driver to
control usb_pcie_grf.
Change-Id: If429629b39d1f68a0fdcb24c6b639f84d513aee5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
