The CONFIG_ANDROID_PARANOID_NETWORK will block network access on ChromeOS.
Disable it on CrOS.
CONFIG_DRM_DMA_SYNC can be used to synchronize CPU/GPU access to a buffer.
Change-Id: Ia979af42b8693161c854e1987122d49c8737b51c
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
These ioctls can be used to synchronize CPU/GPU access to a buffer.
BUG=chrome-os-partner:33438
TEST=add CONFIG_DRM_DMA_SYNC=y, in conjunction with xf86-video-armsoc change,\
run any X application, like xev
Change-Id: I8065ec465ebd0cb6abe128a3e7d92a8f74a88928
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229441
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_gem.c
(cherry picked from cros/chromeos-3.14 commit a847e1f492cbd186116c01a3f56575320dc87152)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Rockchip Socs have GPU, we need allocate GPU accelerated buffers.
So add special ioctls GEM_CREATE/GEM_MAP_OFFSET to support
accelerated buffers.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
BUG=chromium:399935
TEST=With rest of patch set, can boot to UI on eDP
Change-Id: Ia4b13798aac97d16214da7a75a2479e6e334313e
Reviewed-on: https://chromium-review.googlesource.com/222153
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Commit-Queue: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
(cherry picked from cros/chromeos-3.14 commit c29c5a3037e18815937d8af664738e499ada94d1)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.
But the specific GRF register address is different between RK3288
and RK3399, so we need to create a device data to declare the GRF
messages for each CPU chips.
Change-Id: I695d1c729f5605d9e913c82453d311ed97c79a94
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.
Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
That's useful for every PWM controlled to adjust the voltage
regulators.
In the moment. We make savedefconfig to cleanup the rockchuip_cros_defconfig.
Change-Id: I33d68d6cd48310b2da0ea2c3331380e71fc51eee
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This attempts to model commit 063e65397a ("ARM64: dts: rk3399-tb: fix
up the pwm regulator node").
Note that instead of putting a duty cycle of 25000 ns (40 kHz) I've set
a duty cycle of 1667 ns (600 kHz) because I think that's what the TRM
says.
Change-Id: Ifc209eddb20122feec96c5e86f7a14da7d74eb3f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We shouldn't need them in here if you are using the coreboot/firmware.
In general, the cmdline/memory/logic_center will be overwrited
since the coreboot will do that.
Change-Id: I3902ff4eb71891b5c6320bed4355992e699e4835
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Rockchip LCD controller could only output the RGB101010 video
format, so just hardcode the eDP input video format to that.
Change-Id: I39673a35b439656dff7e3358b65ec835c92c4120
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Only the powerofff callback feature is supported through the
rockchip,system-power-controller.
Change-Id: I55e73c05a749edab6c3710e304ee86c03812ab6f
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Thoes file were introduced by Commit bdafdac384
(rk3288 chromium: drm grafic fb support for x11 mali gpu), for now we have the
mainline rockchip drm code, no need those old head files, let's removed them.
Change-Id: I325a5b7981ac5478349f276f8811b1b51e40c564
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This DTS purposely has some comments in "//" style to indicate bringup
work that needs to be done. Don't remove them unless the issues have
been addressed.
The DTS that landed in Rockchip's tree also lost some recent SD work.
Change-Id: I388cfe855b52aa160c1e8d1b468d7e8f35207790
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Check hwc_size after hwc registor config, if check fail, would cause
unexpect problem, iommu crash.
Change-Id: I2e18ea86e9e27e13ccce0737d9d48befcbe345fb
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
We should judge the table.id[mid].code insearch algorithm on matter the
adc value increment or decrement.
Or otherwise, the temperature return the incorrect value in some cases.
[ 1.438589] adc_val=402,temp=-40000
[ 1.438903] adc_val=403,temp=-39375
[ 1.439217] adc_val=404,temp=-38750
...
[ 1.441102] adc_val=410,temp=-40000
[ 1.441416] adc_val=411,temp=-34445
[ 1.441737] adc_val=412,temp=-33889
...
Let's fix it right now.
Fixes commit 020ba95
"thermal: rockchip: Add the sort mode for adc value increment or decrement"
Change-Id: Icac84d06ebf463439ca11db5a19d629b4b2b865c
Reported-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
A GPIO was put in rk3399.dtsi that doesn't belong there. Specifically
this GPIO isn't the same for all rk3399 boards. I presume it belongs in
rk3399-tb.dts, so move it there.
Change-Id: I0b3272655da565eb6b348a33401f7517224db5fa
Fixes: 3ed499f07c ("ARM64: dts: rockchip: rk3399: add usb2.0 phy node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
And removed:
----
-CONFIG_FB=y
-CONFIG_LCDC_RK3368=y
-CONFIG_LCDC_LITE_RK3X=y
-CONFIG_RK_IOMMU=y
-CONFIG_RK_IOVMM=y
----
which are unused on the chromeos.
Change-Id: Icd521b56b6285099d72d3bf25575466792b6d353
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
there will be a build failure when CONFIG_RK_IOMMU
disabled.
Change-Id: Ifd56e39b9cb3021f308f195087304a1d1ec2c599
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>
add pwm init voltage and id for uboot.
fix up the pwms node and add pwm polarity.
Change-Id: I4159c97ae498411ab958c2b1e1223139ac670452
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Portage's linux-info.eclass (in getfilevar_noexec) looks for the
definition of SUBLEVEL, and it doesn't expect 2 definitions. We could
fix the eclass, but let's hack this out for now.
See strongswan's emerge output:
...
* Found sources for kernel version:
* 4.4.6
* 0
/mnt/host/source/src/third_party/portage-stable/eclass/linux-info.eclass: line 388: 6
0: syntax error in expression (error token is "0")
...
Change-Id: I6964e6731ed461ca3a8c4afde0ddfe48e0105627
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/252620
Reviewed-by: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
This config should be opened since the config used for chromeos.
Change-Id: I52dd22b1c1a707e6d27311337a5be6f0041cb7f9
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
