This patch aims to reduce the power consumptiom of usb2 phys
for rk3588. For lowest power consumption, we set the phy1/2/3
enter IDDQ mode by default in uboot spl stage.
IDDQ mode power consumption:
AVCC_1V8_S0 : 0.2mA (0.05mA per phy)
AVDD_0V75_S0: 0.2mA (0.05mA per phy)
VCC_3V3_S0 : 0.2mA (0.05mA per phy)
In kernel, we needs to set the phy exit from IDDQ mode and
reset the phy to enter normal mode firstly. We use suspend
mode instead of IDDQ mode for dynamic power management,
because IDDQ mode will power down all analog blocks and that
cause the usb controllers working abnormally.
Suspend mode power consumption:
AVCC_1V8_S0 : 12.5mA (3.125mA per phy)
AVDD_0V75_S0: 10.3mA (2.575mA per phy)
VCC_3V3_S0 : 0.2mA (0.050mA per phy)
For Type-C0 USB OTG mode, set phy suspend control from GRF,
it can help to reduce the suspend power consumption:
AVCC_1V8_S0 : reduce 5.1mA
AVDD_0V75_S0 : reduce 4.6mA
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I610b95f9bb6da38d25ed2e78b0a87dcb4db8cc38
Enable Low power mode for PCIE by default, the PCIe subsystem will enter
L0s/L1 under hardware control.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9558587f23cf6b4f852ca6b5d1ab5a9f9eb014ca
PCIe Link up state is not only L0(0x11), but also other state like L0s,
L1 and etc.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9b04d01ea38be6423c214f6cb474d045dff235d5
As we don't do it in resume routine, so in order to be better
compatibale with devices, set it to low.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I0613e05f6d35ba7def7eedd902cfaff73d716952
tablet's camera hardware power has been modified,
modify configs to adapt it.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ibc1804c9a1730a8b9d32dafe4cdcb722f603d7a2
Individual port can be suspended or resumed separately.
This can save some time for resuming from deep sleep if
multiports are used.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I44ed4a4a5cbda46425bce13a15809f68856d2174
This patch fix crash in mpp_dev_release.
In multi-instance case the session on deinit is attached to session_detach
and trigger the taskqueue to release session. But the session is
released just after unlock and before trigger then the session and
invalid and the session->mpp is also invalid.
The crash log is shown below:
[71267.807643] Call trace:
[71267.810099] do_raw_spin_lock+0x20/0xd8
[71267.813937] _raw_spin_lock_irqsave+0x28/0x38
[71267.818292] kthread_queue_work+0x2c/0x80
[71267.822298] mpp_dev_release+0x118/0x154
[71267.826219] __fput+0xf4/0x1a8
[71267.829272] ____fput+0x20/0x2c
[71267.832409] task_work_run+0x88/0xb0
[71267.835982] do_notify_resume+0xe8/0x10c
[71267.839902] work_pending+0x8/0x10
[71267.843306] Code: aa1e03e0 d503201f 5289d5a0 72bbd5a0 (b9400661)
[71267.849396] ---[ end trace d8082e9114a3a9da ]---
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: Ib9825de2f1bc9f7999bdfe193aa440fd85d41448
The fifo depth of RK356X/RK3588 writeback is 1920x4/16.
A fifo_throd larger than this value will cause a empty(zero)
writeback.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Id67209f7b162608dcba191ab23cf6eec11e3fc08
The voltage may be changed by system monitor.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I0e3f981fe01e495b9a6b11e9ee333819a1a3ac71
1. change clock rate and read margin only when pd is on.
2. change clock source to normal pll before power down pd.
3. change clock source back to pvtpll and restore clock rate
and read margin after power on pd.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I2028866fdd70909814aaba7ef6d3af3bf764eb87
1. only update voltage when low temperature.
2. set memory read margin only when pd is on.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7a0ae4af45b86c7a08c6ffadccb71a0db3fb44e5
we must wait the video setup ok, and report the plug
event and then startup the audio, if not the vidqpclk
and ipi_clk are off, we can not startup the audio.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: Ie347d02aef7cd696c054ec2cc1eacc77b6f9ff7f
For power consumption saving, disable 12M oscillator in HUSB311 and it
will be enabled automatically when INT occur after system resume. In
addition, if the power of HUSB311 was off in PM suspend, we must reset
the HUSB311 and tcpm port first in PM resume process to ensure the devices
can attach again.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ib845318c5ee2014bd436f21c78e87e17b9433195
When the memory is greater than 4G, dma_buf does not map the RGA2 device.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I7bf62c7d231fbc2c2e928d1387406281701a6269
The configuration of pvtpll and memory read margin will lose if npu pd
power down, and if the source clock of npu comes from pvtpll it will
fail to power up npu pd. so change the source clock to normal pll before
power down, and restore source clock and read margin after power up.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I4a558c51ad061fb99cad384f462065f96ac2f658
As the scmi clk of npu may come from pvtpll, it should power up npu pd
and enable the pclk of pvtpll before set scmi clk. The "assigned-clocks"
in npu node will be set before npu driver probe, at this time the npu
pd may be down, so add "rockchip,init-freq" in opp table node, make
set scmi clk after npu pd is up and pclk of pvtpll is enabled.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I20fc3b6414601134645fa7f157c8ce5db9569232
Add support to change memory read margin according to voltage.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia1939ad7e1c9feef61390290b77316ac99c0c664
Add support to change memory read margin according to voltage when
register system monitor.
Change-Id: Id1d78432b6a83bbb09b4438146a0197dc914347b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add support to change memory read margin according to voltage when
register system monitor.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I04b6464f5c34aa630803cfdd264487fe1eb6ea32
