- Don't require pwrctrl dvs if hw compatible version >= 3.
- Auto parse pwrctrl active pol from GPIO_ACTIVE_{HIGH,LOW} flag.
- Reset pmic and soc when system reboot if required.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I29e60c2a717cee5c9d1e3c6e46ee687352d4a1be
This is use for battery-ipc application with 400w resolution camera
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I5ff04f3063468d4fe60202a1a98003dfb8c870a2
These hdr data is place in first two pages in the front of flash block,
most of the data is filled with 0 which may result in 0/1 data unbalance
and finally accelerate the data bit flip process. So using ff redundant
data pattern for data balancing is more stable for nand devices.
Change-Id: I77a9116a4575b94bc6e4da5334db4eaf3d8bcb83
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Assume the capacity greater than 2GB, and skip the first CMD1
transmission to speed up eMMC initialization.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ic8553873c6d610390db3f031a0a30cdf5df306b6
If supports DMA, make sure clean DMA states for current transfer,
but if not, don't clean it.
Fixes: 37f373979d ("i2c: rk3x: Add dma feature")
Change-Id: Iad8f999c074cb8710f14c7c0ed782b5df690d6ab
Signed-off-by: David Wu <david.wu@rock-chips.com>
rockchip_clocks_loader_protect() always call in arch_initcall_sync().
However, rockchip_clocks_loader_unprotect() is not called when the
DRM driver is not loaded, which assumes that these clocks will always
be enabled.
This may cause the clock to be turned on accidentally. In the case of
ebc, for example, when the ebc driver is enabled and the DRM driver
is not loaded, rockchip_clocks_loader_protect() will enable ebc clk.
In addition, rockchip_clocks_loader_unprotect() will not be called,
meaning that the ebc clock will always be on. However, the ebc driver
will also control the ebc clk, but it will not be able to actually
turn off the clk. The dmc driver will check the status of the clk in
the CRU while working, and it will always find that the clk is on.
This will cause a wrong judgment on the working status of the ebc.
This patch adds constraints to rockchip_clocks_loader_protect() to
protect clocks only when route nodes are available, which means that
the logo is already enabled during the u-boot stage, so it makes
sense to perform clock loader protect.
Change-Id: Ib9efbade547181e86516d19637995569a751fade
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Enable Rockchip RKNPU procfs interface and DMA heap support.
This commit enables two key configurations for Rockchip RKNPU support
on RV1126B platform.
Change-Id: I792b4e9223984d0d2e28639281585f615a015d50
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
If all planes are in rgb format and are in yuv overlay, r2y
conversion is all carried out in bt601. In this scenario, the
input colorspace of post-csc needs to be selected as bt601.
Fixes: 2e4cd35f06 ("drm/rockchip: vop2: update color-encoding selection policy for post-csc")
Change-Id: I2311fe8b0edb3ad44fe98231e723e895df1a3d69
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If the vp dclk clock source corresponding to hdmi is not the
corresponding hdmi phy pll, that resulting in abnormal display
of some resolutions. Furthermore, the use of hdmi phy pll can
support more non-standard resolutions.
Change-Id: I7a39ab2d73e912c596d8e1720d251e89c30b1f3b
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fixes: 4f7e1db593 ("media: rockchip: vicap support use switch device to switch sensor connect to one dphy")
Change-Id: Ieeca97ae618c50e8710c506c24391740092d61b3
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
