on vehicle evb, sdio wifi power on delay recommend 10ms at least.
Signed-off-by: Jason Song <sxj@rock-chips.com>
Change-Id: I0d489b080f0a6323eb14261eaf557e3e3f0e13ee
In some case, the hpd is detected but the aux is not ready. It's
better to detect aux status before get link info from dpcd.
When the dptx send a aux request transaction, the dptx's max
aux timeout value is 3.2 ms, set the timeout value as 10ms
is enough.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id878c0c2c1c5690ac08bad477ea96ac12b674edb
ALSA core blocks userspace for 10 seconds for PCM R/W default.
Consider the situation BT-slave which acts as SLAVE mode, when
BT-master offline sometime, the CLK lost, user have to wait the
core timeout(10s), it's quite bad experience.
This patch allows userspace to override the WAIT_TIME to recover
more quickly from terminal audio stream. especially for stream
which have no mechanism to detect the LINK offline.
Usage:
/# amixer -c 0 contents | grep Wait
numid=43,iface=PCM,name='PCM Read Wait Time MS'
numid=44,iface=PCM,name='PCM Write Wait Time MS'
/# amixer -c 0 cset numid=43 500
numid=43,iface=PCM,name='PCM Read Wait Time MS'
; type=INTEGER,access=rw------,values=1,min=0,max=10000,step=1
: values=500
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I73e98d54388a50672c5ed710db448cd13c0e1098
After FS idle, should wait at least 2 BCLK cycle to make sure
the CLK gate operation done, and then disable mclk.
Otherwise, the BCLK is still ungated. once the mclk is enabled,
there maybe a risk that a few BCLK cycle leak. especially for
low speed situation, such as 8k samplerate.
The best way is to use delay per samplerate, but, the max time
is quite a tiny value, so, let's make it simple to use the max
time. the max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
udelay(40);
Should wait for one BCLK ready after DIV and then ungate clk to
achieve the clean clk. the max BCLK cycle time is:
15.6us @ 8K-8Bit (64K BCLK)
udelay(20);
Increase the max timeout to 1ms to fix FS idle failed. because
it's not enough for 8k samplerate.
rockchip-sai ff810000.sai: Failed to idle FS
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia9da291dd8586236bb32cc0376a6de389f2f0a40
This patch add property 'rockchip,no-dmaengine' to
support register DAI without PCM, and it's usually
used for Multi-DAIs which combine DAIs into a union one.
Change-Id: I4e0da8fae2c692601e05118442218de0f7b4efee
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for keeping BCLK / FSYNC always on.
it's required by some devices, such as HDMI, PA, etc.
For example: on HDMI situation
There are some TVs require maintaining N/CTS packets or AUDS
packets to keep audio logic active, otherwise, the first tone
may be lost.
In order to optimize the user experience, we need to ensure
continuous transmission of N/CTS and AUDS packets from the
HDMI-TX, so that the SINK TV devices can maintain audio logic
activation, promptly process audio data, and achieve the
completeness of the first tone.
We init a 48k I2S-STANDARD clock timing as default.
Change-Id: I298b0ad2d53bdc41927f567c2af481f2a0bd5422
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
There is a issue of stuck during dual-core collabration,
and the hw timeout count will be blocked by default,
and only soft timeout can be triggered to exit.
However, the soft timeout is too loog, so config reg to not mask the hw
timeout.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: If801b8ba3b463094ea497fae829f772de7ade382
In some platform, can not do pmu_idle_request before cru reset.
Resetting without pmu_idle_request while the hw is running
will result in a bus err.
So stop hw first before cru reset to prevent the issue.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I62ace147a0d72adb774fed989b34c7bf22af48ac
This patch add support for Clk-Auto Switch.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2d3b10fcf4cc55ba005d1c9da1049190882f7494
* Support 8-bits width
* Support Mono channel
* Support up to 384k samplerate
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9f1c10bad2bfb9a3beee1dd91508158e79da2492
Modify the micorvolt of vdd_arm to support the new hardware.
Signed-off-by: Zhichao Guo <zhichao.guo@rock-chips.com>
Change-Id: Id4e102c0a72898c27e0f2547e08c5d5095edfb76
If no need to activate the decompress flow, using CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
should be better.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic9750ab71cc0d7c5beddd41f11ab71aa4df69bff
dsi->connector.funcs may be NULL, because drm connector may be
implemented in drm bridge which attached dsi.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Id8668a70405ff41d770784cb9a5db3b16d92f3a3
Including:
kbase_device_kinstr_prfcnt_init(),
kbase_device_kinstr_prfcnt_term(),
kbase_device_io_history_init(),
kbase_device_io_history_term.
To resolve compilation errors when CONFIG_DEBUG_FS is not enabled.
Change-Id: Ibeaf97bd9fdbbb45308160e11c4dbb386a0dea71
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
1. get the value of pvtpll@0.9v from otp.
1. adjust opp-table by pvtpll value.
2. adjust opp-table by mbist-vmin.
3. adjust opp-table when low temperature.
Change-Id: Idc0c0e811c80d1b9b51d4a4f5c7176c546558386
Signed-off-by: Liang Chen <cl@rock-chips.com>
