This reverts commit 7a03fe6f48.
We need a new patch for dw_mmc to deal with phase policy in case of
new register layout, otherwise it will break phase stuff for some
case
Change-Id: Iffb7a6dbe0b17d27c2cca4b2b99ddbc4e0736f18
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add ctrl-base for rk3399 to make emmc-phy work.
Change-Id: Iffb7a6dbe0b17d27c2cca4b2b99ddbc4e0736f15
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Need to control phy's digital block before enabling pll and
waiting for it into locked state.
Change-Id: I04037f5496fd5c1ef4e24853eb32b43ce326ff01
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch adds ctrl-base which points to the digital block
to setup phy pll enabling.
Change-Id: I922dd7574229fda6b2ee51ca6ed1d7852ef87d30
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
To slove the issue found on evb2 for hs400
[ 1.526008] sdhci: Secure Digital Host Controller Interface driver
[ 1.526558] sdhci: Copyright(c) Pierre Ossman
[ 1.527899] sdhci-pltfm: SDHCI platform and OF driver helper
[ 1.529967] sdhci-arasan fe330000.sdhci: No vmmc regulator found
[ 1.530501] sdhci-arasan fe330000.sdhci: No vqmmc regulator found
[ 1.568710] mmc0: SDHCI controller on fe330000.sdhci [fe330000.sdhci]
using ADMA
[ 1.627552] mmc0: switch to high-speed from hs200 failed, err:-84
[ 1.628108] mmc0: error -84 whilst initialising MMC card
[PATCH reviewing: https://patchwork.kernel.org/patch/9010851/]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I7641a3c095bb893a56f18fa3faa88ca179f3dae3
req_range is declared as a u64 to cope with overflows in the
multiplication of two u32. As both req_power and power_range are u32,
we need to make sure the multiplication is done with u64 types.
Change-Id: I1aea92f12e48338be2681a9b2ba84756b6cc8cf8
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit f9d038144a)
The commit 17e8351a77 consistently use int for temperature,
however it missed a few in trip temperature and thermal_core.
In current codes, the trip->temperature used "unsigned long"
and zone->temperature used"int", if the temperature is negative
value, it will get wrong result when compare temperature with
trip temperature.
This patch can fix it.
Change-Id: I4b31f577a6142bc02f8e0deae79ab2ff7c8bd978
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit 1d0fd42fa3)
The dynamic power consumption of a device is proportional to the
square of voltage (V) and the clock frequency (f). It can be expressed as
Pdyn = dynamic-power-coefficient * V^2 * f.
The coefficient represents the running time dynamic power consumption in
units of mw/MHz/uVolt^2 and can be used in the above formula to
calculate the dynamic power in mW.
Change-Id: Ib208ff2f83ee45911e846f940952d765ae8c974e
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit 3be3f8f36e)
this mode is used for the case just like two LCD output and display
kernel logo when power on.
Change-Id: I188b95bc638a66338de3401fd7b9eec049d7071a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
because hwc will open fb0 to fb5, so the logic state is enable,
this will lead to iommu page fault when switch screen.
Change-Id: I8bc34887a62338049d1d526e37a2595122265046
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
In most case, we use the VPLL directly for HDMI or DP, and the
the frac dclk will bring the big jitter for dclk. So we don't need
to use the dclk_vopx_frac.
Change-Id: I0d27e5fcb8b4c9a28c0102074c1d6da9426386f4
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The rk3399 hdmi phy is supplied by the vpll directly and needs to adapt
that frequency depending on the selected resolution on the hdmi output.
For the hdmi-phy the vpll frequency is supplied unchanged without
any dividers being present there.
The vpll also is one of the sources the general display clock of the
visual output processor (vop) and as it is somewhat special for
display operations possibly also the preferred pll source. Here a divider
is available between the pll-mux and the vop clock, so that this part
can adapt the resulting frequency if needed.
So to keep the vop clock in line with the target rate, set the newly
introduced CLK_KEEP_REQ_RATE flag for the dclk_vop clocks on rk3399.
(am from https://patchwork.kernel.org/patch/8993771/)
Change-Id: Iba9a179b764472f22d7531eb0c662dcd982433d4
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Given a hirarchy of clk1 -> [div] -> clk2, when the rate of clk1 gets
changed, clk2 changes as well as the divider stays the same. There may
be cases where a user of clk2 needs it at a specific rate, so clk2
needs to be readjusted for the changed rate of clk1.
So if a rate was requested for the clock, and its rate changed during
the underlying rate-change, with this change the clock framework now
tries to readjust the rate back to/near the requested one.
The whole process is protected by a new clock-flag to not force this
behaviour change onto every clock defined in the ccf.
(am from https://patchwork.kernel.org/patch/8993761/)
Change-Id: Ie2636710cb4e66815ee45b28ec86eeaaa47c55c7
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The req_rate property seems to be made to hold the rate requested through
clk_set_rate. Currently it gets initialized in clk_init to the clocks
current rate and then adapted in clk_set_rate calls. Orphan clocks and
their children get initialized to a rate of 0 and req_rate never gets
re-set when these lose their orphan-status.
Initializing req_rate to the clocks rate also is unintuitive as it just
copies the value that is already in the rate property and also looses the
information if a component actually requested a specific rate.
So separate the requested rate and only set it in clk_core_set_rate_nolock
when a real rate gets requested. The users of the req_rate __clk_put and
clk_set_rate_range that adjust a clock based on that value use req_rate
at first and fall back to rate if no rate had been requested now.
(am from https://patchwork.kernel.org/patch/8993751/)
Change-Id: I9e345e1e9d0c101d5c3c7064b6c2d2724f9eac4f
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
As the pervious discussed, disabled the edp node for dts. Otherwise
you connected the mipi panel will show white since the edp will force
to use the extend screen.
Change-Id: I3e716f4a9d92d4faae5d7a12d792c71fe16f489e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The gpu can't work with chromeos since the regulator has not enabled.
Okay, the gpu can work for chromeos with rk3399 evb2 on now.
Change-Id: If23affff151a99206b86c2a3f40c21752bdc2d54
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
fix warning:
warning: 'ret' may be used uninitialized in this function
Change-Id: I743ed9788366322beeceddd556fae0c2a7cdd463
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
RK3399 hdmi register layout is similar with rk3288 and rk3368, so most
code can reuse. but hdmi resign is upgrade from 20 to 21 so it has a
little diffrence. and the hdmi phy clk is Independent from dclk too.
Change-Id: I83b30c92d9572fc9ceaf52777d224e5cec1823be
Signed-off-by: xuhuicong <xhc@rock-chips.com>
fix up the warning:
drivers/regulator/lp8752.c: In function 'lp8752_buck_set_mode':
drivers/regulator/lp8752.c:93:2: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized]
Change-Id: Iee9f69791bbcea2e6b3a16713b76e93cfc0a2b67
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Seperate power-on timer for rkvdec and vpu when they are not
in combo mode (definitly independence).
Before this patch, h/w power off schedule will be interrupted
by the other h/w, and power off will be triggered when h/w
still running a task.
Change-Id: I29124e90afccc727d2e7a04098727aa4a2c3e8bb
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
It will enable the devfreq thermal that's generic devfreq cooling
mechanism through frequency reduction for devices using devfreq.
This will throttle the device by limiting the maximum allowed DVFS
frequency corresponding to the cooling level.
Change-Id: Ia017ecf46599700382b9604e375193135f7d1d24
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Let's use unlock/lock around phy APIs as them will call
mutex which is sleepable casuing failure of kernel debug
check.
Change-Id: Ic7670bfc9ed763cc9bdec53f85f553bc0be1416c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
rgb/edp/hdmi/mipi pin_pol is removed after (e5683dd FROMLIST:
drm/rockchip: get rid of rockchip_drm_crtc_mode_config), that
is wrong.
This patch re-add those pin_pol config.
Change-Id: I46f3e32ad405f4b6e2f76110757248e8516693c4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
enable_time is controlled by capacitance connected to Pin SS,
it described more detailedly in mp8865 datasheet Page 15.
Capacitance is 12nF now.
Change-Id: Ib604a4e109db7ab125104e5cf3067864fefb6fe0
Signed-off-by: Zain Wang <wzz@rock-chips.com>
There is a path that use vskiplines with non-initialize.
That would cause vop abnormal behavior.
Change-Id: I53c6c575d6acc16aeae761dbb4867f3bc8bfe5ce
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
On Async atomic_commit callback, drm_atomic_clean_old_fb will
clean all old fb, but because async, the old fb may be also on
the vop hardware, dma will access the old fb buffer, clean old
fb will cause iommu page fault.
Reference the fb and unreference it when the fb actuall swap out
from vop hardware.
Change-Id: I585786884295060efdaef0a00c3cbd75244399d7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The series vop of VOP_FULL framework support area plane, such as
RK3288 and RK3399, one group of area planes share same hardware,
reuse the hardware on different scanout time, this design is
useful to support mulit planes with low hardware consume.
Change-Id: Ie53211ce9ed22d03f7668637efbb7c95d9a8eb5b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The plane hardware is used when the display scanout run into plane active
scanout, that means we can reuse the plane hardware resources on plane
non-active scanout.
Because resource share, There are some limit on share plane: one group
of share planes need use same zpos, can't not overlap, etc.
We assume share plane is a universal plane with some limit flags.
people who use the share plane need know the limit, should call the ioctl
DRM_CLIENT_CAP_SHARE_PLANES, and judge the planes limit before use it.
Change-Id: Iecc3d8e7f1ce29d567cdbad689ba4dbad3d594e1
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
We need to take care of the vop status when use
rockchip_drm_crtc_mode_config, if vop is disabled,
the function would failed, that is terrible.
Save output_type and output_mode into rockchip_crtc_state,
it's nice to make them into atomic.
Conflicts:
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
drivers/gpu/drm/rockchip/inno_hdmi.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
Change-Id: I43c49a92b2b9df02ce8a055bd16948b400ab0f47
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/8844321/)
On the RK3368 SoC, support the APB timers for rockchip platform.
Change-Id: I2bee09c4140994d3d2e23f1820663230d82547de
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c840f28bbf)
