This patch can change phy internal 45 Ohm resistance accord to
reference resistance. The larger the reference resistance, the
greater the internal resistance, and accordingly, high speed
eye diagram amplitude will become lower.
The maximum adjustable range of the reference is +-20% of the
default value (200 Ohm).
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ibd746283c06609b944fa2a148066ba0a661e761a
This patch adds a binding that describes the Rockchip USB 2.0
PHY designed by Naneng.
Change-Id: I7cca8bbf0a395baaebb4867681acd4f73004c1b0
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
The USB2.0 OTG PHY of RV1126/1109 which is designed for lower power
consumption provides only 8.8mA current source on DM. Multiplied
by 45 Ohm host termination resistance, voltage is about 400mV.
If the threshold voltage of host is greater than 400mV, the high
speed handshake will fail and SoC communicate at full speed. So
swing calibration is necessary.
We use gpio to control the 220 Ohm pull-up resistor to provide additional
current. Experiments show that the voltage of chirpK can be increases
to about 600mV.
Change-Id: I8b41054af4732569dbc8185bc3d3d4a2ba83cd6a
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
The USB2.0 OTG PHY of RV1126/1109 which is designed for lower power
consumption provides only 8.8mA current source on DM at chirpK state.
Multiplied by 45 Ohm host termination resistance, voltage is about 400mV.
If the threshold voltage of host is greater than 400mV, the high speed
handshake will fail and SoC communicate at full speed. So swing
calibration is necessary.
Because we use this interface for swing calibration. This patch also
disable phy calibration in setting host mode for rockchip platform.
Change-Id: Ic1c8bb6aac95b3d0d61d99becb4facea1bbecb25
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
Gt917s is a panel adapter board with ili9881d matching touch IC.
At the same time, init delay Ms 80 instead of 10, is to solve the
problem of high probability of not displaying due to incomplete
reset when the hardware of the panel adapter board is changed.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I17eff7fdd140a7d6f82e8991ad2bdd7765d43a73
This reverts commit 955bb70bf1.
Fix the following changed report by build_abi.sh for GKI
'struct phy_ops at phy.h:56:1' changed:
type size changed from 512 to 576 (in bits)
1 data member insertion:
'int (phy*)* phy_ops::cp_test', at offset 448 (in bits) at phy.h:70:1
there are data member changes:
'module* phy_ops::owner' offset changed from 448 to 512 (in bits) (by +64 bits)
17 impacted interfaces
Change-Id: I5f163b804aaff2fe9c6e3a7c054de3f8df0c791c
Signed-off-by: William Wu <william.wu@rock-chips.com>
The rockchip_u3phy_cp_test() is used for USB3 compliance
test, and it depends on the cp_test of phy_ops which will
be dropped later, so we remove rockchip_u3phy_cp_test()
directly.
As a side effect, we need to use io commands to set the
USB3 enter compliance test mode instead of host_testmode
for RK3328 USB3 PHY.
Change-Id: Ie756b22f5bb89e146ad971f2668111a4733ff892
Signed-off-by: William Wu <william.wu@rock-chips.com>
The combphy_u3_cp_test() is used for USB3 compliance test,
and it depends on the cp_test of phy_ops which will be
dropped later, so we remove combphy_u3_cp_test directly.
As a side effect, we need to use io commands to set the
USB3 enter compliance test mode instead of host_testmode
for RK1808 USB3 combphy.
Change-Id: Iac7d9a4c6b0d2a74c284586f5dcbb48925691a91
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch remove debugfs directory and host_testmode which
cause the following error:
ERROR: "xhci_set_link_state" [drivers/usb/dwc3/dwc3-rockchip-inno.ko] undefined!
We remove the code of host_testmode directly, because it
depends on the phy_cp_test() which will be dropped later.
As a side effect, we need to use io commands to set the
DWC3 Host enter compliance test mode instead of host_testmode
for RK3328 USB3.
Change-Id: Ie0b1fac63fd6458f07ad30edadc7c4c27486e894
Signed-off-by: William Wu <william.wu@rock-chips.com>
When I test the uac gadget function, I find that the uac
gadget out transfer may stop expectedly and the alsa buffer
will be empty which results to input/output error.
In some cases, we will get an endpoint event
DWC3_DEPEVT_XFERINPROGRESS and the event status is
DEPEVT_STATUS_MISSED_ISOC, and the original code try to issue
an EndTransfer command. After the EndTransfer is completed,
we will get a XferNotReady event. However, it will fail to
giveback the req to the udc gadget driver due to an additional
request unmap operation.
To fix this problem, this patch return directly in kick transfer
if there are isochronous endpoints and retry to transfer next time.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I80a8e7c0caa9129e5736bbf89909662c2f3ed4fe
There are some differences between hardware V12 and v10
1.Power:
The buck1 of rk809 supplies power to NPU and vepu
The discrete power supplies power to logic
2.Reset signal of camera:
The reset signal of csi rx0 is control by gpio1_D5,
The reset signal of csi rx1 is control by gpio2_A0.
Change-Id: Ib290939c9a3a47efaeabfbadbc796126e0cbf279
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
The USB2.0 OTG PHY of RV1126/1109 which is designed for lower power
consumption provides only 8.8mA current source on DM. Multiplied
by 45 Ohm host termination resistance, voltage is about 400mV.
If the threshold voltage of host is greater than 400mV, the high
speed handshake will fail and SoC communicate at full speed. So
swing calibration is necessary.
We use gpio to control the 220 Ohm pull-up resistor to provide additional
current. Experiments show that the voltage of chirpK can be increases
to about 600mV.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I387ae1840959540ff9ca22db26896def0e890619
This patch will enable id interrupt for otg port when the property
vbus-always-on is set in dts.
If vbus is always on, bvalid interrupt won't make sense and be
disabled. But we cat change id state to switch drd mode by software.
Change-Id: I69fc3f00430dfd73835c6e99694d8d7c72c60c8c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
By bypass charge detect module, about 140uA current can be saved
on USB_AVDD_1V8 power supply when suspend. Notice that bandgap
current can not be turned off, so there is still about 165uA
current.
This patch also remove the tuning in phy resuming, because the power
of phy is always on and registers does not need to be configured
again.
Change-Id: If13d3741e3b01289c1bd0294d6e6d88278c4654c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This patch remove the clks manegement in phy operations and keep the
clks always on. Keep the clks on can avoid many errors such as USB480M
clk abnormal output and EHCI controller error.
Change-Id: If201106d432d05e8fc5f63d595a67524e2183b5c
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
According to VOP_VERSION register on rv1126, the
major is 0x2, minor is 0x0b.
Change-Id: Ie8f3a91d839bcd042a655881302e9b43f6f297d5
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
1. read clock setting using the common code from dtsi.
2. clock enable/disable, all devices using the same function.
3. clock frequency set to two levels: normal and advanced.
4. according to specific requirements, the frequency is set
level instead of the value.
Change-Id: Idcf8e0f49987df20f3eb2574aff316e507f82cfe
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
The sequence of operations is as follows:
1. disable the sleep pin function
2. modify the sleep pin polarity
3. delay 3 32k clock cycle
4. select the sleep pin function
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: If6df2b2f190951abe9bb31fbd18d9af47e145038
Get the calibration parameters for each chip by reading the OTP,
Calculate temperature using calibration parameters.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I05cfb65ae95dcefc7fc52ed91326c7da9d27de55
