- the original config is too strict to satisfy general usage.
- adds CONFIG_SND_SOC_ROCKCHIP_PREALLOC_BUFFER_SIZE for flexible
buffer size.
Change-Id: I1f060269cb1887c17a2cd83701f0263993be8ec7
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
when hdmi plug out or switch hdmi resolution, vop output timing
maybe still at 4k resolution, but dclk will be set to 27M immediately,
this will lead to one frame time change from 16.6ms to
(594 / 27) * 16.6 = 365ms.
drm will dump the following log, this looks uncomfortable, so we use
rockchip_drm_atomic_helper_wait_for_vblanks to instead of
drm_atomic_helper_wait_for_vblanks to cancel the dump log when mode
update, and retain the debug warning log for every frame commit.
[ 31.415329] ------------[ cut here ]------------
[ 31.415383] [CRTC:56:crtc-0] vblank wait timed out:1201:1201
[ 31.415498] WARNING: CPU: 2 PID: 366 at drivers/gpu/drm/drm_atomic_helper.c:1433 drm_atomic_helper_wait_for_vblanks.part.21+0x2c0/0x2d4
[ 31.415529] Modules linked in:
[ 31.415573] CPU: 2 PID: 366 Comm: composer@2.1-se Tainted: G W 4.19.80 #1337
[ 31.415601] Hardware name: Rockchip RK3328 EVB avb (DT)
[ 31.415633] pstate: 60400005 (nZCv daif +PAN -UAO)
[ 31.415661] pc : drm_atomic_helper_wait_for_vblanks.part.21+0x2c0/0x2d4
[ 31.415696] lr : drm_atomic_helper_wait_for_vblanks.part.21+0x2c0/0x2d4
....
[ 31.423867] Call trace:
[ 31.423904] drm_atomic_helper_wait_for_vblanks.part.21+0x2c0/0x2d4
[ 31.423939] drm_atomic_helper_wait_for_vblanks+0x1c/0x20
[ 31.423969] rockchip_atomic_commit_complete+0xb0/0x130
[ 31.423997] rockchip_drm_atomic_commit+0x1d4/0x230
[ 31.424032] drm_atomic_commit+0x50/0x68
[ 31.424067] drm_mode_atomic_ioctl+0xbe0/0xcb0
[ 31.424100] drm_ioctl_kernel+0xa0/0xe4
[ 31.424133] drm_ioctl+0x318/0x4a4
[ 31.424168] do_vfs_ioctl+0xbc/0xdb4
[ 31.424201] ksys_ioctl+0x78/0xa8
[ 31.424225] __arm64_sys_ioctl+0x1c/0x28
[ 31.424262] el0_svc_common.constprop.1+0xb4/0x168
[ 31.424288] el0_svc_handler+0x20/0x78
[ 31.424320] el0_svc+0x8/0x340
[ 31.424349] ---[ end trace af4d2af5b5fb7553 ]---
Change-Id: I5988882380fa91b7527999ac2cd5ae13cfc88a8b
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
LZ4 uncompress is faster than LZO. And same as arm64.
Save about 177 ms boot time on rk3126-bnd-d708-avb.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I59b008f8b6e36bd790310cace653c4e54800e438
The regulator may not ready when probe video driver, then the video
driver will probe failed. We need probe video driver again if
get_regulator() return -EPROBE_DEFER, so return -EPROBE_DEFER to
the probe.
Change-Id: Ibd60f0397af7e5d8ef79d05b44d40fd66722d53b
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Sometimes, the random pool initialization is too slow in reocvery mode,
use hw_random to speed up it.
Change-Id: Iabc37548ef03e60dca9707126750629efafbfe6d
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
fireprime is using rk818, which need a battery node for fuel gauge,
or else the input current will be limit to 500mA.
Change-Id: Ie80dbc103d1ac57b704235a9b618b7e9db44c953
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The address@88000000 is out of memory on rk3128-fireprime, so remove
the cma region@88000000, just delete the property <reg>, so that
system will alloc cma region automatically.
Change-Id: I2b9fdf1cd19d9fcecd59421fd551d709f9054cae
Signed-off-by: Liang Chen <cl@rock-chips.com>
ttyS2 and fiq debugger don't use the same uart2
Change-Id: Ibb9db5ff84d334d77787ea6f39a0802ba489781c
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
In order to support 420MHz for gpu and 125MHz, 50MHz for gmac.
Change-Id: I2b0e3edbf08850555c5bd4bc1d063c8923d54bda
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
It doesn't support 400MHz, but support 420MHz.
Change-Id: Ife31469307912f83919b02b532acde91cc0f19ce
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The default parent of i2s_src is 200MHz CPLL, it doesn't meet
the constraint of fractional divider that denominator must be
20 times larger than numerator.
Change-Id: I986525ca7a92cb5883facd1b6e89079398302856
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Enable otg to apply dwc2-controller and u2phy_otg driver.
Change-Id: I5d5b7623ff18b1bf14f8b6e91620bfb88770cd63
Signed-off-by: David Wu <david.wu@rock-chips.com>
If this clock does not enable, the otg controller is
working abnormally.
Change-Id: Ic08043e19d3ef1ed8cfb35267828ff317fb438f6
Signed-off-by: David Wu <david.wu@rock-chips.com>
1.Decrece reserved IDBlock from 16 to 8
2.Decrece print info
Change-Id: I69443b0f2381f061176d6f2cf32497f644564093
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Extern all controller low layer driver APIs in rkflash_api.h
2.Register dev when controller node is probed;
3.APIs rkflash_dev_xxx for dev register in rkflash_blk.c, support:
rkflash_blk: SLC Nand blk dev;
rkflash_blk: SPI Nand blk dev;
rkflash_blk: SPI Nor mtd dev;
spi_nand_mtd: SPI Nand mtd dev;
spi_nor_mtd: SPI Nor mtd dev;
Change-Id: I5423fead6b6343d1ab94303d30d486dea74b166c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
