Commit Graph

854029 Commits

Author SHA1 Message Date
Alex Zhao
2d7c6370ea net: rockchip_wlan: rtl8723cs: fix some bugs
1.enable CONFIG_TXPWR_BY_RATE_EN
2.add 80211R support
3.fix EFUSE_MAP_PATH

Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I4bbe4f78c707639e3f89070b8d6566d2ae897c9f
2020-05-25 18:20:34 +08:00
Alex Zhao
6350c43fae net: rockchip_wlan: rtl8821cs: enable CONFIG_RESUME_IN_WORKQUEUE
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I5db0646d20840fcc3d01b4af8b0a5259ee8871d4
2020-05-25 18:20:34 +08:00
Alex Zhao
ff1b9f0113 arm64: dts: rockchip: rk3368-tablet: set sdio default sample phase to 90
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I2702cab3288a230616ab3d0f149b59f3d50f3232
2020-05-25 18:20:34 +08:00
Tony Xie
d0a76dd65c PM / devfreq: rockchip_bus: remove the autocs keyword.
1、remove the autocs keyword.
2、use cfg-val instead of timer-us in rk1808.dtsi
3、remove bus-soc node in px30.dtsi

Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Change-Id: I0f4563476ad7e08ba8dd9d02097eb4448d024ecd
2020-05-25 18:20:34 +08:00
Andy Yan
e0d873e815 drm/rockchip: Convert MCU cmd from rgb565/rgb666 to rgb888
VOP wrongly treated MCU cmd as normal rgb data and pass it
to dither module when output mode is rgb565/rgb666, then
the cmd output from vop io is changed.

Here we convert the MCU cmd data from rgb565/rgb666 to rgb88,
so that we can get the original cmd data after dither module.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I7919dfb9d4f6279b82636d68cd7b211047bf1b46
2020-05-25 18:20:34 +08:00
Andy Yan
790c812deb drm/rockchip: Disable dither for mcu interface
VOP MCU interface can't work right when dither enabled.
(1) the MCU cmd  will be treated as rgb data then changed by
    dither algorithm
(2) the dither algorithm works wrong in mcu mode

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I401907e306928d590fddef9099f4a96dbfc7e0f2
2020-05-25 18:20:34 +08:00
XiaoDong Huang
7d70d14c7f ARM: dts: rockchip: rv11xx-evb-v10: enable rockchip_suspend node
Change-Id: I9c2a83cf64f3667d75912b3a118012d9566edffe
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2020-05-25 18:20:34 +08:00
XiaoDong Huang
d178e135e1 soc: rockchip: support rv1126 pm config
Change-Id: I91aaaab020dd04362c9f5ca3c585d22181df8be6
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2020-05-25 18:20:34 +08:00
XiaoDong Huang
21d52845a5 ARM: dts: rockchip: rv1126: add rockchip-suspend node
Change-Id: I948b343220030982b019f63150cddcb2971dbe36
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2020-05-25 18:20:34 +08:00
XiaoDong Huang
4702a46f04 dt-bindings: suspend: rv1126: add sleep mode config defines
Change-Id: I795ada46df0ecba55d675d709dcf2bf61265b43e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2020-05-25 18:20:33 +08:00
XiaoDong Huang
31d20737b0 ARM: dts: rockchip: rv11xx-evb-v10: fix sleep_pin config
Change-Id: Idacd5b3257d53aae8aa71eb464b1bc71580db55c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2020-05-25 18:20:33 +08:00
Nickey Yang
41fd458194 ARM: dts: rv11xx-evb-v10: adjust panel power on sequence for ili9881d panel
According to spec
The minimum time for VDDI/VSP on to reset high is 5ms,
The minimum time for reset to first command is 10ms.
So adjust them to save panel init time.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ic6c4240c1d3657d05192a5f13eb4eb469e932191
2020-05-25 18:20:33 +08:00
Tao Huang
962d22e3c2 ARM: dts: rockchip: enable initcall async for rv1126-evb-ddr3-v10-tb
Change-Id: Ic8328ab176448a5794412811c4f9a8f43fd890a7
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2020-05-25 18:20:33 +08:00
Zefa Chen
26861abfa6 ARM: dts: rv11xx-evb-v10: add cam_ircut
Change-Id: Ia4bdd66fb87476f0c21f97f3da5ffe0c635dbbe0
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
2020-05-25 18:20:33 +08:00
Cai YiWei
1e9c1e6669 media: rockchip: adjust isp and ispp init order
Change-Id: I6a84f99d37a4f4114aa7288903c5cfaa82e3adb0
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2020-05-25 18:20:33 +08:00
Finley Xiao
9d089eb791 ARM: dts: rv1126: Add assigned-clocks for rkvenc
Change-Id: I5590d91146ab13071f6b79e73980a72eaa087c6e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 18:20:33 +08:00
Finley Xiao
a23ba6b788 ARM: dts: rockchip: rv11xx board: Add regulator for rkvenc
Change-Id: If7cdd3173204606ae44fc532b5b89f50d23fc013
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 18:20:33 +08:00
Finley Xiao
6676e307fe ARM: dts: rv1126: Add opp table for venc
Change-Id: I80970b66fd133cef7eab53af27d7dbedd930933a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 18:20:33 +08:00
Yiqing Zeng
f4ee1007d5 media: rockchip: ispp: set rkispp_m_bypass link flag to 0 by default
Signed-off-by: Yiqing Zeng <zack.zeng@rock-chips.com>
Change-Id: I353a3504d7d7dcbeabbdaa97fe24809aa345b5fd
2020-05-25 18:20:33 +08:00
Jianing Ren
a55e37ec7e phy: phy-rockchip-naneng-usb2: modify opmode when suspend
According to the Naneng Specifation, opmode should be set
to 2b'01 Non-driving mode when suspend.

Change-Id: Ib43ef64af2e7fc413125f68ebeb72743f23e0050
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
2020-05-25 18:20:33 +08:00
Zefa Chen
4241f3fb73 media: i2c: imx347 support 12bit
Change-Id: I50c91ef498b5a6f6ecc99ed0ceae60d615c00b54
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
2020-05-25 18:20:33 +08:00
Allon Huang
a566137c9c ARM: dts: rockchip: link rkcif with ar0230 for rv11xx-evb-v10
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I2f5dbc957c86a9a463122466b2a48ed71f66dd64
2020-05-25 18:20:32 +08:00
Zhichao Yu
82218a42eb ARM: dts: rockchip: unlimited logging to /dev/kmsg for rv1126-evb-ddr3-v10-tb
printk.devkmsg={on,off,ratelimit}
	Control writing to /dev/kmsg.
	on - unlimited logging to /dev/kmsg from userspace
	off - logging to /dev/kmsg disabled
	ratelimit - ratelimit the logging
	Default: ratelimit

Signed-off-by: Zhichao Yu <zhichao.yu@rock-chips.com>
Change-Id: I69f5f4804990247b35e9aea3106e1536b8dc3be7
2020-05-25 18:20:32 +08:00
Sugar Zhang
17954bb1cf ARM: dts: rv1126: Move camera device node into rv11xx-evb-v10
Change-Id: I51f4291875e0a8811768152f7e1bf49e0fbaf248
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-05-25 18:20:32 +08:00
Allon Huang
f85f0c0277 ARM: dts: rockchip: rv1126 add rkcif node
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I42cb9fb5b69c085fa24bdc9e5c8a9e8c04ada7dc
2020-05-25 18:20:32 +08:00
Allon Huang
832a2e67a9 drivers: media: platform: rockchip: cif: single dvp channel can sample data for rv1126/rv1109
fix reg address conflict between rv1126/rv1109 and other chips

Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I12c0291a24068ea385369d8c4aa371385992f8cd
2020-05-25 18:20:32 +08:00
Cai YiWei
5e7bbc163f media: rockchip: ispp: fix try_fmt result
Change-Id: I9085e9e96e1d35499c0a3f6a340119d3f98783ba
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2020-05-25 18:20:32 +08:00
Zhichao Yu
c2af3d7d97 ARM: dts: rockchip: modify romfs decompress memory for rv1126-evb-ddr3-v10-tb
We need more memory for romfs decompress. Currently, with NPU the romfs
size is 18MB.

Signed-off-by: Zhichao Yu <zhichao.yu@rock-chips.com>
Change-Id: Id473db768fc1994c606b3de9320f939da7123d11
2020-05-25 18:20:32 +08:00
Huang zhibao
dcdc6a52c5 ARM: dts: rockchip: rv11xx-ai-cam set usb0 tx fifo to be reallocated
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I89517ed8f8d54f2e58a749ca35476e0a8f729495
2020-05-25 18:20:32 +08:00
Tao Huang
1885551fac clk: rockchip: rv1126: No register DDR clk when CONFIG_ROCKCHIP_THUNDER_BOOT=y
Change-Id: Ifaad38a4ca27ca06b311dc738f4cd1e04a4da465
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2020-05-25 18:20:32 +08:00
Tao Huang
19c5ebf9a8 media: i2c: os04a10: Call os04a10_i2c_driver_init() early when CONFIG_ROCKCHIP_THUNDER_BOOT=y
Change-Id: I3df679a8b665dabdb510cf8c252e88a96cc4b44e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2020-05-25 18:20:32 +08:00
Cai YiWei
60a5b6699e media: rockchip: fix isp and ispp stream status error
Change-Id: Icb4de811190d8d3f2fe797acee64cf58ee0a55f5
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2020-05-25 18:20:32 +08:00
Hu Kejun
4e7672dde0 media: rockchip: ispp: fix set core_ctrl of shp is wrong
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: Ie00ba8baa238b34a19b3f50c309705800861d25d
2020-05-25 18:20:32 +08:00
Hu Kejun
bbeb26a30a media: rockchip: isp: fix mp/sp can not get picture in rdbk mode
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: Ibf303e6031d4d31a7cc281dff844c1e0e6b3354f
2020-05-25 18:20:31 +08:00
Zefa Chen
4629acc757 media: i2c: os04a10 change
1.add digital gain control
2.add delay time to 12ms after power_on
3.os04a10_global_regs write in start_stream
4.default used 12 bit

Change-Id: I8c9918c3188608b19d73bf23f83ec02dda1b926e
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
2020-05-25 18:20:31 +08:00
Cai YiWei
874374348b media: rockchip: isp: fix dmatx align and dmarx dt
csi to ddr is work unit
config damrx data type if dmatx no work

Change-Id: If82bfd06c09b725aa159c13a700c02c34e79a253
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2020-05-25 18:20:31 +08:00
Zefa Chen
a7ab3b8acb media: i2c: imx347 fixed frame rate to 20fps
Change-Id: Ifcb541be432278d889139cc7941febc8bba42cc5
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
2020-05-25 18:20:31 +08:00
Cai YiWei
d56f480f7b media: rockchip: ispp: fix fec no work
Change-Id: I2b6974ea191180678401ee129ab55c5d3e12836d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2020-05-25 18:20:31 +08:00
Hu Kejun
26a88b6472 media: rockchip: isp: fix sof is not report in normal mode after run hdr
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: Ia7560bfd2c15c111ce8fd95b540114457af08731
2020-05-25 18:20:31 +08:00
Hu Kejun
c9a04358e5 media: rockchip: ispp: change fec mesh number
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: I68bf7bfdd080486083b5177ade48ed2dcb8d1fd9
2020-05-25 18:20:31 +08:00
Hu Kejun
8d1d0cfb64 media: rockchip: isp: change ldch mesh number
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: I2ce3fb8f996347d26ddd398e9066d9dc82707429
2020-05-25 18:20:31 +08:00
Huang zhibao
47a2e88510 ARM: dts: rockchip: add ai-cam-ddr3-v1 dts for ai cam ddr3 board
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ic9a504a3a8fe9465101a353640254259c952ae6b
2020-05-25 18:20:31 +08:00
Huang zhibao
8845e6c07f ARM: dts: rockchip: rv11xx-ai-cam enable display_subsystem
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I76de315ad86791ed052ec71959d874642349683d
2020-05-25 18:20:31 +08:00
Huang zhibao
10f90e2b5c ARM: dts: rockchip: add rv11xx-ai-cam dtsi
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I14cfb33f81a2931640bee9cf78cb1127eff7163b
2020-05-25 18:20:31 +08:00
Hu Kejun
3818f0768a media: rockchip: isp: get iq statistics data in irq for rdbk mode
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: I6570dbf65ca790646daf3fcc8b81be461b66931f
2020-05-25 18:20:31 +08:00
Hu Kejun
f21184b34d media: rockchip: isp: send l/m/s hdr frame together in rdbk mode
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: Iec5b8ac5d7a2c0916aa8d68f6e505c3d87eb1046
2020-05-25 18:20:31 +08:00
Hu Kejun
25612c2f15 media: rockchip: isp: fix sof event is not right
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: Ia992a21b92282294f5702e79bfc5d5effb089180
2020-05-25 18:20:30 +08:00
Finley Xiao
9002395928 soc: rockchip: pvtm: Add support for RV1126 SoCs
This adds the necessary data for handling pvtm on the RV1126.

Change-Id: I07a0c97874ff4d3d536cb93908710381da558af2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 18:20:30 +08:00
Elaine Zhang
9daa92de87 clk: rockchip: rv1126: add RV1126_CSIOUT_FRAC_MAX_PRATE for mipicsi_out
Change clk_mipicsi_out2io_fracdiv input limit from 1200MHz to 300MHz.

Change-Id: Ia6adff4faa9cf14931a631dcd7415a77d6df4142
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-05-25 18:20:30 +08:00
Finley Xiao
6bf099f383 ARM: dts: rv1126: Move pvtm clocks and resets properties to child node
Change-Id: Iea685566df8930e817e8bb86c9c73e541f7ee8a8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-05-25 18:20:30 +08:00