We don't need to reference the pmugrf/grf in the clock driver any more.
Change-Id: Ibda203163c84ab4004e1225e5868267024069199
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
These are not gating default when the SoC startup, so we don't need
to re-enable them.
Change-Id: I956a31345fe7f24b973db6c9e49d87a2988ac7d6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
A virtual device like "drm" call iommu_attach_device may fail.
Current only judge if a device has "group", this is not enough,
"group->iommu_data" is needed
Change-Id: I1a66d6016dfef867d83aa4cccaf223ced4e07161
Signed-off-by: Simon <xxm@rock-chips.com>
As the rk3399 SoCs requires initial configuration for tsadc clock
frequency. The tsadc can be specified in a device tree node through
assigned-clocks.
The tsadc clock needs 500KHz~800KHz frequency to work on rk3399 SoCs.
We can add the assigned-clock to prevent the firmware
or loader has *not* set the division frequency from the source clock.
Change-Id: Ieb4cd5aad7d299baab20a9fb9d39211fe00896ff
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch adds the rockchip,grf to match the driver.
Change-Id: If477634fd38f1ebc539ade6c620a63d0cfee9111
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This adds the grf property to handle the tsadc power sequence on
rk3399 SoCs.
The rk3399 tsadc can work with this patch on now.
while true; do grep "" /sys/class/thermal/thermal_zone[0-1]/temp;sleep .5; done
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41666
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
Change-Id: I0155826bddf0017ea4985920268b333a20278bbe
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
there is a time window between __mmc_send_status() and time_afer(),
on some eMMC chip, the timeout_ms is only 10ms, if this thread was
scheduled out during this period, then, even card has already changes
to transfer state by the result of CMD13, this part of code also treat
it to timeout error.
So, need calculate timeout first, then call __mmc_send_status(), if
already timeout and card still in programing state, then treat it to
the real timeout error.
Change-Id: I7499d3d41711ea5abe6baec780d2988dc60dfc5b
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 3bbb0deea6)
Normally the timeout clock frequency is read from the capabilities
register. It is also possible to set the value prior to calling
sdhci_add_host() in which case that value will override the
capabilities register value. However that was being done after
calculating max_busy_timeout so that max_busy_timeout was being
calculated using the wrong value of timeout_clk.
Fix that by moving the override before max_busy_timeout is
calculated.
The result is that the max_busy_timeout and max_discard
increase for BSW devices so that, for example, the time for
mkfs.ext4 on a 64GB eMMC drops from about 1 minute 40 seconds
to about 20 seconds.
Note, in the future, the capabilities setting will be tidied up
and this override won't be used anymore. However this fix is
needed for stable.
Change-Id: Ifd327b7c534a346f3537432d7bce7d8f1aebef3f
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org # v3.18+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 9951362479)
This patch fixes the incorrect conversion table.
The Code to Temperature mapping is updated based on sillcon results.
Change-Id: If8ae3f5fb59786a8db8bf79276ecea44ab92ffc9
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Set dwc3_0 in peripheral only mode until Type-C function is
ready, and then we can set dwc3_0 in drd mode.
Change-Id: I0ccb92db97244d7a34dd17c58757fc5aa1b11dac
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This reverts commit 0b622df349.
arm pmu driver do not support PPI in two
cluster well. So drop it.
Change-Id: I69f43ad1703589805c7e86749badda8bf802d51a
When rk_iommu_attach_device or rk_iommu_detach_device be called, the second
parameter "dev" represent the device who own the iommu, so it is not resonable
using "dev" for devm_request_irq's first parameter. To avoid potential error,
we must use iommu device itself "iommu->dev" instead, the same as devm_free_irq.
Change-Id: Id9f4097d6f1b916308475854dcf75ce86d9494fc
Signed-off-by: Simon <xxm@rock-chips.com>
1. Add a new compatible for rk3399;
2. Support gpio operation for vbus-drv.
Change-Id: I2eb1ac377db0bcb907d009c56fba22f1951c128e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
On some systems regulators need to do special actions on suspend/resume.
These get set from the generic regulator_suspend_prepare and
regulator_suspend_finish functions so these should be called from the
psci suspend ops as well.
Change-Id: I6fbf7b39ceae936ed5bd9df6719ccd3cd360840f
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
RK3399 dwc3 has some hardware properties, which is platform
dependent, including the following properties:
1. Set PHYIF to 1 to use 16-bit UTMI+ interface;
2. Clear ENBLSLPM to 0 to disable sleep and l1 suspend;
3. Clear U2_FREECLK_EXITSTS to 0;
4. Clear DEV_FORCE_20_CLK_FOR_30_CLK to 0;
5. Clear DELAYP1TRANS to 0;
Change-Id: I85de326e3c2177c66966f1239bcab838df01492d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether delay PHY power change from P0
to P1/P2/P3 when link state changing from U0 to U1/U2/U3
respectively.
Change-Id: I23e33f8b13001d6f86d6473ad43a261d9bda8f79
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Fix add critical clock for PMUCRU too late in the rk3399_clk_init. It
will be crash if there is one clock want to disable its parent which is
the PPLL.
Change-Id: I3fa236ab78571c8c8ec5d423228d00dbb02f24e6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
this patch corrects the interface adc/dac control register definition
according to datasheet.
Change-Id: I0777577d365140b642141596112b662d3a80538b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org broonie/sound.git for-next
commit 653aa46452)
In order to lower the temperature, lower the voltage.
Change-Id: Iae2d103c88ab5b72c3d003c1f84f74e1694c7e1e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0.
Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
interface is hardware property, and it's platform dependent,
so we need to configure it in devicetree to set the core to
support a UTMI+ PHY with an 8- or 16-bit interface.
And according to dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must set to the required values for the usb2 phy interface.
Change-Id: If1c636edc6be3c9a79b4b0b89737a925d8dd3abe
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Change-Id: I84ea6eeccb9fc2ea6d13ef586f1166d5fa132606
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
* linux-linaro-lsk-v4.4-android: (477 commits)
arm64: vdso: Mark vDSO code as read-only
ARM/vdso: Mark the vDSO code read-only after init
x86/vdso: Mark the vDSO code read-only after init
lkdtm: Verify that '__ro_after_init' works correctly
arch: Introduce post-init read-only memory
x86/mm: Always enable CONFIG_DEBUG_RODATA and remove the Kconfig option
mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings
asm-generic: Consolidate mark_rodata_ro()
Linux 4.4.6
ld-version: Fix awk regex compile failure
target: Drop incorrect ABORT_TASK put for completed commands
block: don't optimize for non-cloned bio in bio_get_last_bvec()
MIPS: smp.c: Fix uninitialised temp_foreign_map
MIPS: Fix build error when SMP is used without GIC
ovl: fix getcwd() failure after unsuccessful rmdir
ovl: copy new uid/gid into overlayfs runtime inode
userfaultfd: don't block on the last VM updates at exit time
powerpc/powernv: Fix OPAL_CONSOLE_FLUSH prototype and usages
powerpc/powernv: Add a kmsg_dumper that flushes console output on panic
powerpc: Fix dedotify for binutils >= 2.26
...
set clk_cpul:816M clk_cpub:1008M when clk tree init
Change-Id: I8f493ce8479fc670aa05d651db5be354d6870c98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
With this defconfig which inherits from rockchip_defconfig,
ChromeOS boots up to command line.
Change-Id: I646fea9b26d9c235da16d0d2b559290ee5029a12
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
1. Compatible "rockchip,rk3399-usb-phy" support to RK3399;
2. Add host_drv_gpio optional property for usb2.0 vbus control.
Change-Id: Idfc6898ca2c519c46dae66d396f501b38e8d73bd
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
Change-Id: I116b66c3b417cfecc968414db9912813a0ef2c5d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
