Afbc only check the new state, If new atomic state has no plane state,
But old plane state has afbdc, the afbc check would be wrong, and cause
display abnormal.
Change-Id: I078241149c302ca137bec69f310555c7c37c6992
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
enable the following peripherals:hdmi/wifi/
hdmi_sound/spdif/sdio/sdmmc/hym8563(rtc);
enable the integrated phy for gmac by default.
Change-Id: I92f10e02c5c783c044ab4a080f6f553458d5a971
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
At this point in time, dsi->slave is always NULL, so fix it.
Change-Id: I4f5a75d2547b1083751fcbbb0c7e0c568dc19028
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Fixes: d6dfcd07b7 ("drm/rockchip: dw-mipi-dsi: analyze the platform parameters in the probe function")
Change-Id: Iecf9532f52a1b27ea063556701f840329881a2e2
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Fix issue like, rx_running is set 1 after first start rx.
But rx_running is still 1 after stop rx, which causes
dma can not be started when second start rx.
Change-Id: Id2f3a535da1b3609e8af287edbcc2e25fb7ae922
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
In the most common use case, the Synopsys DW UART driver does not
set the set_termios callback function. This prevents UPSTAT_AUTOCTS
from being set when the UART flag CRTSCTS is set. As a result, the
driver will use software flow control as opposed to hardware flow
control.
To fix the problem, the set_termios callback function is set to the
DW specific function. The logic to set UPSTAT_AUTOCTS is moved so
that any clock error will not affect setting the hardware flow
control.
Change-Id: Iea1e99512f0818eaa1642d25eb1ad02da049e8c6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
To fix issue like this:
dma-pl330 ff6d0000.dma-controller: pl330_update:1733 Unexpected!
dma-pl330 ff6d0000.dma-controller: DMAC halted!
The root cause is DMA clk is closed when DMA interrupt is
in service. This may happen, as follow:
1. When pl330_terminate_all is called, and set pch->active false,
power_down is true, call pm_runtime_put_autosuspend.
2. Then pl330_tasklet is called, if power_down is also true, call
pm_runtime_put_autosuspend again.
3. DMA is opened again, because the autosuspend is asyn, it may close
the DMA clk. If DMA interrupt is coming, it causes the issue.
Change-Id: Ib1feb508c16afb4bc9ced0c3660f2b6b4a19c068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The scaling list buffer handle under the pps unit
will be translated into the DMA address for the device,
but the processing is done under the kernel, so the
iommu of the device won't be invoked. We don't need to
cache it.
Using the standard kernel method is enough to access
the memory under the kernel space, so all the map to
kernel methods of the memory management are removed.
A few steps for memory mapping are also merged in
this patch.
Change-Id: Ia3f6f38568aed8021baff757720453c4eea03b90
Signed-off-by: ayaka <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
if power-invert exist the panel power need to disable ldo when
power on and enable ldo when power off otherwise it's opposite.
example:
panel {
...
power-invert;
...
};
Change-Id: Ida5718d01044873cdd7c753c4e8b872dc1e52099
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
because currently mclk is handled by codec side, so the
associated pinctrl should be handled by codec too.
Change-Id: I0611b7a291351a20f72b5124c501dc79d92787d6
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
because currently mclk is handled by codec side, so the
associated pinctrl should be handled by codec too.
Change-Id: I55db6e9a0181cae0cb414b9dcacae7ff0214b50c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Initialize default format for current stream and set stream state
to 'READY' in case of streaming on by user without passing format
to driver. Default format will be overridden by VIDIOC_S_FMT.
Implement VIDIOC_G_FMT and application can get the format info
of current stream now. This will become necessary when enable
'--set-fmt-video' option of v4l2-ctl test suite,
Set bytesused of each plane to its real size to prevent confusing.
The IO mode of vb2 queue 'VB2_DMABUF' is now supported.
Change-Id: Id52da502df8aea796b3405ebf472541a394afd80
Signed-off-by: Jacob Chen <cc@rock-chips.com>
When import dma_buf to rga driver, dma_map_sg will always do
cpu cache sync, it cause low performance.
Actually we don't want to do cpu cache sync on this context,
So set rga device with dma-coherent to skip cpu cache sync.
Change-Id: Ie256db6a072481953befafb5b8003b9c1e713436
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
When import dma_buf to rga driver, dma_map_sg will always do
cpu cache sync, it cause low performance.
Actually we don't want to do cpu cache sync on this context,
So set rga device with dma-coherent to skip cpu cache sync.
Change-Id: Idfeb0de2e1d92873dcbd560cec40a4f9f8807013
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
If the gpio base is started from 1000, the "gpio = 0" will
be invalid, that can avoid something unforeseen. The real
pin number is "gpio number - 1000".
If you cat the gpio log, you will see the log like this:
rk3399:/ # cat d/gpio
GPIOs 1000-1031, platform/pinctrl, gpio0:
gpio-1004 ( |bt_default_wake_host) in lo
gpio-1005 ( |power ) in hi
gpio-1009 ( |bt_default_reset ) out lo
gpio-1010 ( |reset ) out lo
gpio-1011 ( |? ) out hi
GPIOs 1032-1063, platform/pinctrl, gpio1:
gpio-1034 ( |int-n ) in hi
gpio-1035 ( |vbus-5v ) out lo
gpio-1036 ( |vbus-5v ) out lo
gpio-1045 ( |enable ) out hi
gpio-1046 ( |vsel ) out lo
gpio-1049 ( |vsel ) out lo
gpio-1056 ( |int-n ) in hi
GPIOs 1064-1095, platform/pinctrl, gpio2:
gpio-1083 ( |bt_default_rts ) in hi
gpio-1090 ( |bt_default_wake ) in hi
GPIOs 1096-1127, platform/pinctrl, gpio3:
gpio-1111 ( |mdio-reset ) out hi
GPIOs 1128-1159, platform/pinctrl, gpio4:
gpio-1150 ( |? ) out hi
gpio-1153 ( |vcc5v0_host ) out hi
gpio-1156 ( |hp det ) in hi
Change-Id: I744ddc1df6075b0a044d65c65622e2a59f3a332e
Signed-off-by: David Wu <david.wu@rock-chips.com>
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the driver supports clocks
properly, we can drop this.
Change-Id: I91d0a5c000ed7215bf55dbc871e175ac79a1cd2a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
When DRAM frequency greater than or equal to this setting value,
the function of auto power-down will disable.
Change-Id: I0c7faee045ff00de0dc36adc45e21389c41aa81f
Signed-off-by: YouMin Chen <cym@rock-chips.com>
If frac clk parent rate is PLL rate, but still lower
than frac rate*20, not allowed fractional div.
Change-Id: I09c93e1d8f32c0a4e345057964d58505b1477204
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
clk_uart4_src default parent is 24M,does not satisfy the
fractional divider must set that denominator is 20 times
larger than numerator.
Change-Id: I21fd9866794e052414a6fdf1d64840ac2a0bb8f2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The dmc driver supports changing min_freq and max_freq according to
system status and vop bandwidth at present. But even if user changes
governor to userspace, the ddr frequency may also change constantly.
This patch adds a new dmc_ondemand governor which doesn't chang min_freq
and max_freq, it can also support changing ddr frequecy based on usage,
system status and vop bandwidth. So users can set their own frequency by
the userspace governor.
Change-Id: Ib731f29a6ded3b7f05e60cbae4f858e6beeac9da
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
