The address of wdt0 and wdt1 are swapped, let's fix it.
Change-Id: I715d181b8984a72ad234d4c1389154f15b60738a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Get opp table from device node for rk3399 dmc table.
Change-Id: I689078d60ebdadf0954b60de70d05bc56a8d6597
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.
Change-Id: I4cc6bd9218f6fe0ae09d79c23516c6dbdaa59af2
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This patch adds the documentation for rockchip rk3399 dmc driver.
Change-Id: Icaff8fa2173ded5c64a08e877d32a8eca1a0c3be
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.
Change-Id: I85efe7f626e636606508fdd171b14275591c0612
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This patch adds the documentation for rockchip dfi devfreq-event driver.
Change-Id: Ib5704cdef0c7a53abe3afda126cb1a1adba43b3a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Change-Id: Ib743ffb642fe0c7c0a3b7db14389803595d868b3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Since evb2 couple with ES1, the power consumption is large enough to
shutdown device in some case.
Let's reduce it's support lists to make things simple.
Change-Id: I145aa0c6a21e41b3c8e6ff32fd15839baa15f81e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's disable it as the auto link training of PCIe
take quite long time without add-in card or M.2
devices available.
Change-Id: I4a48a44574b68da75845a6e614a9970bb5d6685b
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Fix them for matching what the new drivers want.
Change-Id: I6ce43379ab9cf3d274b6b414ec014e431db588b7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add support for the Rockchip PCIe controller found on RK3399 SoC platform.
Change-Id: Ic924a0defaef195575beba4dfc92c33b6b5bc3e7
[Shawn: manually backport to 4.4 with some minor changes]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Several host bridge drivers iterate through the list of bridge windows to
request resources. Several others don't request the window resources at
all.
Add a devm_request_pci_bus_resources() interface to make it easier for
drivers to request all the window resources. Export to GPL modules (from
Arnd Bergmann <arnd@arndb.de>).
Change-Id: I4b89f0739d66d6027bfd2a01e9e93f5218ade617
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 950334bcf1)
This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Change-Id: Ieba96d9cdf0d96302f38d29789615e2ec93f3440
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
These must be translated from the values in the TRM by subtracting 32,
which has not been done.
Change-Id: I8d26bd63d39009b60b310e7ccbcd5de814863861
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
When connected with type-c to standard-a cable, inno phy will
generate an interrupt before setting the state of typec to host,
which result in detecting of battery charger. This patch change
the state to host before interrupt happen.
Change-Id: I6a2e15c264bd6729c3b8d23af23ad15145559b20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Add a binding that describes the Rockchip PCIe controller found on Rockchip
SoCs PCIe interface.
Change-Id: Ifb84320315c06759612f2b3d9b2b6ff3e1e5cb1e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.
Change-Id: I18940e940e0c951d3e2d6bb3b2131a37727a430d
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If pwm polarity was configured with different values at uboot,
the enable_conf would not be configured correctly.
Change-Id: I55b9ccc262382951a8a82810f1be74ce9460f266
Signed-off-by: Zhou weixin <zwx@rock-chips.com>
1. modify clock-names, according to Heiko's suggestion, clock names
should always be in the scope of the device block (named after what
it supplies), and clock-names are always meant from the perspective
of the individual ip-block.
2. remove unnecessary clocks, refer to rk3399 TRM, aclk_usb3 is the
parent of aclk_usb3otg0/1 and aclk_usb3_grf, and we will enable
aclk_usb3otg0/1 and aclk_usb3_grf, so don't need to enable aclk_usb3
again. In addition, the aclk_usb3_rksoc_axi_perf clk is used for usb3
performance monitor module which we don't use now, so don't need to
enable it.
Change-Id: I1d50a72d1523b8b70f1e5f388dc357807131dd7c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
When do Rx compliance test, PHY is in loopback mode, we
observed that Rx test failed with long cable, and it was
found that equalizer adaptation is not happening properly.
With rx_eq_training forced from PMA, the equalizer adaptation
working fine and Rx test can pass. The root cause is that
the Rx REE component will be turned off when control data
is being received by default PHY configuration. So we need
to unmask REE control data by setting REE control data mask
register, and with this patch, equalizer training will happen
based on the signal coming from controller only.
Change-Id: Ic4fca1045d92381470588c4afccff0cc7318ab4c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
userspace will set several frame after vop suspend, so the kernel back
buffer will be freed and after resume vop will read a freed buffer and lead
to post empty, so we close all win before suspend, after resume vop will
display black until userspace set a new frame.
Change-Id: I6648861d2162f221e7fbf85d2361ad245e7b88aa
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
