Commit Graph

596696 Commits

Author SHA1 Message Date
Huang Jiachai
39ac2a068d video: rockchip: vop: 3399: update for cabc
If enable cabc function, close auto gating, because cabc and auto gating
can't enable at the same time, in addition cabc open and close will lead
to splash screen, so when close cabc, we just set stage up and down to 0.

Change-Id: Ia4561d6adafa956c26d1921caecc7eed97dd218a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
2016-09-30 15:39:13 +08:00
zhangjun
190390b40e arm64: rockchip_defconfig: enable rk_headset
Change-Id: I6644e71b9a1fc5a10a711b55fab3056c4152105c
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
2016-09-30 15:31:52 +08:00
Jianhong Chen
a2b672fd1b power: rk818 charger: fix otg supply on/off error
As we register regmap irq to manage rk818 irqs, it should
not enable/disable irq by modifying register directly. And
check otg on/off line state before setting new state.

Change-Id: I45d45d62bea05b1c489337ac7f3334fbafcd4166
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
2016-09-30 15:29:49 +08:00
Jianhong Chen
fffb397c49 power: rk818 charger: remove suspend and resume callback
CHG_CVTLIM_INT is default disabled yet

Change-Id: I07123ad023322e7a88a3b992988980498256b284
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
2016-09-30 15:22:32 +08:00
Jianhong Chen
ef3cb3a604 mfd: rk808: add RK818_IRQ_CHG_CVTLIM into rk818 regmap irq
Change-Id: Iae2bf8e6aa86c0fd82b6905c9f37fffe2c719479
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
2016-09-30 15:22:08 +08:00
Elaine Zhang
fc6056b76f clk: rockchip: rk3399: fix up the spi softrst ID
fix up the spi3 and spi5 softrst ID.

Change-Id: Ib8870ef765284e04674ce80acf0b4702ed77cebc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-09-29 16:39:02 +08:00
chenzhen
ef0f93264c MALI: midgard: RK: not to power off all the pm cores
This is a workaround for the issue that
"400M, 500M and 600M of clk_gpu needs high vdd_gpu",
according to "6.1" of Mali Application Note
"Potential glitches on Power Domain interfaces".

Change-Id: I58daa3cf796802f073f67bacb62734516be76205
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
2016-09-29 16:38:10 +08:00
Zorro Liu
7be137a0f4 dt-bindings: screen-timing: Add RAYKEN RK055AUWI5003 single channel MIPI screen dts
Change-Id: I2e2e9b30bdb19be765cecd38f31e651872d03e82
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2016-09-29 11:44:44 +08:00
Zorro Liu
f8452e4ab4 dt-bindings: screen-timing: set h381dln01 75fps, add screen-width and screen-hight
Change-Id: I88166845112a2c17c86a44a6c43bdea4ac26347f
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2016-09-29 10:38:06 +08:00
Elaine Zhang
d8cbb1aec8 clk: rockchip: rk3399: fix up the dclk_vop1_div parents
if the dclk_vop0_div allow CLK_SET_RATE_PARENT for VPLL,
the dclk_vop1_div parent is not allowed in vpll.

Change-Id: I9973014e8ed2fcf1c351e3f62c00040677391ff7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2016-09-29 10:22:44 +08:00
zhangjun
904247b6d7 rk_headset: re-enable driver/headset_observe/
Change-Id: I84a05b94894b0240d8dd6fbd9ef7bc693b933da9
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
2016-09-27 18:14:36 +08:00
Jacob Chen
9a60f35e5e arm64: dts: rk3399: add power-domain property for edp
Change-Id: Ic6df7a80cbb1572725d4b8cbb7b3074bcd28d13c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
2016-09-27 10:17:30 +08:00
Huibin Hong
7f436b9cf7 ARM64: dts: rk3399-android: Set ramoops_mem size to 0xf0000
Change-Id: I3c0c4a51ed2ff19e4baad17349e3e87efc43a2f6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2016-09-26 19:04:07 +08:00
Huibin Hong
c26a25a7fd ARM64: dts: rk3399-android-next: Set ramoops_mem size to 0xf0000
Change-Id: I69c2416fb07b4364f1e02fe21be351771b1b6c6b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2016-09-26 19:04:06 +08:00
lanshh
245ae3931a drivers: iio: imu: fix initial screen offset when switch app
Change-Id: Ia65b4b5e03b712d0c69546d69ea7b4364f30b05b
Signed-off-by: lanshh <lsh@rock-chips.com>
2016-09-26 18:35:39 +08:00
Huibin Hong
087633170d rk_fiq_debugger: Reset and set uart to loopback mode before init
The uart may be reinitialized when resume, if uart is in busy
state, which would fail to configure the baud rate. So reset
and set uart to loopback mode can make sure uart is in idle
state.

Change-Id: I54d9ac8de1531cd06da8c223583cd2e330178eff
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2016-09-26 18:33:23 +08:00
Bin Yang
97ff73ffbc arm64: rockchip_defconfig: enable hall sensor mh248
Change-Id: Id2818a07865e114f45f57b2bb5a70bb886d7fc38
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
2016-09-26 18:09:06 +08:00
Huang, Tao
c682b23147 input: sensors: hall: do not enable hall default
Change-Id: I773b1cd05b8cf5aef26035f356732b3a487fc6e0
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2016-09-26 16:03:13 +08:00
Meng Dongyang
ad23b5c8bd usb: dwc3: unregister extcon notify if probe fail
When the pointer of hcd is NULL, dwc3 driver will probe again. In this
case the notify sync function will issue "Bad mode in Synchronous Abort
handler detected" error if the extcon notify is not unregisted before
next probe. This patch add unregister extcon notify function and
unregister extcon notify when hcd is NULL.

Change-Id: Id55ce4280518e0c7e36a64133e38189bb4a7d29e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2016-09-25 16:12:08 +08:00
David Wu
63e8d019d4 input: keyboard: rk_keys: Add support for configuring adc drift value from DT
If the adc drift value is 70, some keys maybe report twice, because
the range of adc_value +/-70 is overlapping other keys' adc range.
So it is better configuring adc drift value from DT, that also can
support more keys at a adc channel. The default adc drift value is
70, if it does not get the drift value from DT.

Change-Id: I46cef235094116d4f03af5e5c0cd3a6dfe7e8b0d
Signed-off-by: David Wu <david.wu@rock-chips.com>
2016-09-24 14:36:06 +08:00
Meng Dongyang
7f7a1313ef usb: u2phy: add support for otg function
In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.

Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2016-09-23 21:41:32 +08:00
Meng Dongyang
5c2303a10b usb: dwc3: fix logical error during controller probe
The probe function of usb controller will remove hcd struct in host
or otg mode, while the hcd is alloced after xhci driver registed. So
there is a logical error if xhci driver is registed after usb
controller and it results in the pointer of hcd point to NULL. This
patch make usb controller probe again if hcd point to NULL.

Change-Id: I659f86decac59fca610b355356fc971b3a86d4be
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2016-09-23 18:26:06 +08:00
zain wang
fe2fc59322 mfd: fusb302: correct the wrong pointer type used in regmap_read
used unsigned int pointer that regmap_read wanted instead of unsigned char
pointer

Change-Id: I89f838144a4d27a3bf695232acc4dbbe920863bf
Signed-off-by: zain wang <wzz@rock-chips.com>
2016-09-23 17:13:41 +08:00
xiaoyao
3527e57090 HACK: mmc: core: fix switching clk 400K to 52/200M status error
Change-Id: I56285d306e8e3a52039a7612fae666ed40117a4a
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:11:07 +08:00
xiaoyao
65b3ac3a8c mmc: sdhci-of-arasan: add sdhci_arasan_voltage_switch for arasan,5.1
Per the vendor's requirement, we shouldn't do any setting for
1.8V Signaling Enable, otherwise the interaction/behaviour between
phy and controller will be undefined. Mostly it works fine if we do
that, but we still see failures. Anyway, let's fix it to meet the
vendor's requirement. The error log looks like:

 [   93.405085] mmc1: unexpected status 0x800900 after switch
 [   93.408474] mmc1: switch to bus width 1 failed
 [   93.408482] mmc1: mmc_select_hs200 failed, error -110
 [   93.408492] mmc1: error -110 during resume (card was removed?)
 [   93.408705] PM: resume of devices complete after 213.453 msecs

Change-Id: Icc5457355c3f57b84bd6073f0c4e01350bcc9ee6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:10:28 +08:00
xiaoyao
5b0edb353a mmc: core: changes frequency to hs_max_dtr when selecting hs400es
Per JESD84-B51 P69, Host need to change frequency to <=52MHz after
setting HS_TIMING to 0x1, and host may changes frequency to <= 200MHz
after setting HS_TIMING to 0x3. It seems there is no difference if
we don't change frequency to <= 52MHz as f_init is already less than
52MHz. But actually it does make difference. When doing compatibility
test we see failures for some eMMC devices without changing the
frequency to hs_max_dtr. And let's read the spec again, we could see
that "Host may changes frequency to 200MHz" implies that it's not
mandatory. But the "Host need to change frequency to <= 52MHz" implies
that we should do this.

Change-Id: I1dc9f5fa8dc217e033fc4b1689ca1b0204c294c0
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:08:41 +08:00
xiaoyao
09c5c21b64 mmc: core: switch to 1V8 or 1V2 for hs400es mode
When introducing hs400es, I didn't notice that we haven't
switched voltage to 1V2 or 1V8 for it. That happens to work
as the first controller claiming to support hs400es, arasan(5.1),
which is designed to only support 1V8. So the voltage is fixed to 1V8.
But it actually is wrong, and will not fit for other host controllers.
Let's fix it.

Change-Id: I982bf34b3d305123ab7debd858e60f2454123c24
Fixes: commit 81ac2af657 ("mmc: core: implement enhanced strobe support")
Cc: <stable@vger.kernel.org> 4.4# +
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:07:55 +08:00
Ziyuan Xu
a586397e80 mmc: core: don't try to switch block size for dual rate mode
Per spec, block size should always be 512 bytes for dual rate mode,
so any attempts to switch the block size under dual rate mode should
be neglected.

Change-Id: I6ede0d8fd6c7b8e4903a51c1c2a1b96d350bd2e2
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:06:40 +08:00
xiaoyao
44c69f1dc0 UPSTREAM: ARM64: dts: rockchip: update rk3399.dtsi for emmc&phy
Change-Id: I97948c250f63423c5a7f305cfaa3a10b190f736f
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:05:31 +08:00
xiaoyao
b56e9be360 UPSTREAM: phy: update phy-rockchip-emmc.c upstream version
Change-Id: I9f582f28492a301fb281a3dce92421abb782c822
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:04:58 +08:00
xiaoyao
aa1988136c UPSTREAM: mmc: update sdhci-of-arasan.c upstream version
Change-Id: I72285f9d962f7399428102db483ad3c3ed19f998
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:04:17 +08:00
xiaoyao
b86a5126f5 UPSTREAM: mmc: core: update mmc.c upstream version
Change-Id: Ie67d23ca74708467d5af01b4ca801efa5dcd2f51
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
2016-09-23 17:04:06 +08:00
Zhou weixin
d5c5e4bcc1 arm64: dts: rockchip: adjust the backlight level table on rk3399 mid
Change-Id: Ia5a7ca623d4db8b4fbd32fab45d5c4b924413bee
Signed-off-by: Zhou weixin <zwx@rock-chips.com>
2016-09-23 16:04:13 +08:00
zhangjun
62971dabc8 arm64: dts: rk3399-sapphire-excavator-edp: disable hdmi audio
due to ff8a0000.i2s can't bound to card "rockchip,hdmi" and
"rockchip,cdn-dp-fb" at the same time

Change-Id: Ie43bf882f0eacb6e87d10ba5eba0fd38dbb5462e
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
2016-09-23 15:09:10 +08:00
wuliangqing
1fc37088db ARM64: dts: rk3399-mid: update for emmc&phy
Change-Id: I4dffff1475a6e05344ef1ea4cb9bd662e32e53fc
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
2016-09-23 15:07:22 +08:00
wuliangqing
bbd165be73 ARM64: dts: rk3399-vr: update for emmc&phy
Change-Id: I59c767a37ef072132c3b81fe1029763202420593
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
2016-09-23 15:07:05 +08:00
Wu Liang feng
8f2c7e7cd7 usb: dwc3: fix logical errors and improve stability for rockchip platform
1. put clks err handle at the end of probe.

2. register extcon notifier after dwc3 core initialized successfully.

3. try to get extcon cable state in probe, this can avoid to
   lose the first extcon state notifier.

4. fix pm runtime handle and disable clks in remove operation

Change-Id: I0bea71206801139efb37a835b65562c051a2072e
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
2016-09-23 15:03:29 +08:00
Nikita Yushchenko
756d9ad548 UPSTREAM: regmap: fix deadlock on _regmap_raw_write() error path
Commit 815806e39b ("regmap: drop cache if the bus transfer error")
added a call to regcache_drop_region() to error path in
_regmap_raw_write(). However that path runs with regmap lock taken,
and regcache_drop_region() tries to re-take it, causing a deadlock.
Fix that by calling map->cache_ops->drop() directly.

Change-Id: I55c6d3ed490c47e8b3f5ca774d051a700f707b6e
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from git.kernel.org broonie/regmap.git for-next
 commit f0aa1ce625)
2016-09-23 10:05:03 +08:00
Mark Yao
60a514699d drm/rockchip: vop: support interlace display
Change-Id: I39c66ff90d85c2ee7bc8495ed313c359f0d457d6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2016-09-23 10:03:40 +08:00
wuliangqing
46ee4a0ac4 ARM64: dts: rk3399-vr: add n-key for return
Change-Id: I06654319d61d57eabe7556d45501cf081cdd6b39
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
2016-09-23 10:00:04 +08:00
David Wu
a55a3e72a8 i2c: rk3x: Fix variable 'min_total_ns' unused warning
This patch fixs the following warning:
drivers/i2c/busses/i2c-rk3x.c: In function 'rk3x_i2c_v1_calc_timings':
drivers/i2c/busses/i2c-rk3x.c:745:41: warning: variable 'min_total_ns' set but not used [-Wunused-but-set-variable]

Change-Id: I99da5c5dc80da040eb5333bdf204a71de472a332
Reported-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-23 09:43:04 +08:00
David Wu
62f63ea380 i2c: rk3x: Fix sparse warning
This patch fixes the following sparse warning:
drivers/i2c/busses/i2c-rk3x.c:888:17: warning: cast truncates bits from constant value (ffffffffff00 becomes ffffff00)

Change-Id: If4ffda2f57ce967a6824765093823bd7ff75ebe3
Reported-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-23 09:40:47 +08:00
Jacob Chen
339fab0f14 arm64: configs: add COMPAT configuration
I don't know why it was removed by former savedefconfig.
Maybe I make mistakes..

Change-Id: I4d852320c5b57ba9c72b7ef2981b6b66d76ba0b8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
2016-09-22 20:50:49 +08:00
Jacob Chen
a8e6476d04 arm: dts: add ramp delay to vdd_gpu for rk3288
for mali devfreq

Change-Id: I561fe2db1a38bafcf56db7e8991172d6031da41a
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
2016-09-22 20:50:12 +08:00
Mark Yao
ce4accc725 drm/rockchip: vop: support csc convert for win0/1
Change-Id: I7be5dfb7d2711de5a5aeed730aea0ffd9e080945
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2016-09-22 20:46:47 +08:00
Mark Yao
c762b0ce17 drm/rockchip: vop: init vskiplines on scale calculate
Here is a Bug on scale calculate:
   int vskiplines = 0;
   maybe vskiplines = 2 on yrgb scl_vop_cal_scale
   maybe vskiplines not update on cbcr scl_vop_cal_scale.
   Then cbcr path would get vskiplines = 2, that is unexpect.

Change-Id: Iaeb0d125c7bbcfb95fe32005ef5c938703d03ed4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2016-09-22 20:46:34 +08:00
Tero Kristo
c1834e4eb4 UPSTREAM: regulator: core: remove lockdep assert from suspend_prepare
suspend_prepare can be called during regulator init time also, where
the mutex is not locked yet. This causes a false lockdep warning.
To avoid the problem, remove the lockdep assertion from the function
causing the issue. An alternative would be to lock the mutex during
init, but this would cause other problems (some APIs used during init
will attempt to lock the mutex also, causing deadlock.)

Change-Id: I4a4367f3ebc9c7a00d6a08b547f2cebecd600483
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 07c5c3ad98)
2016-09-22 20:12:28 +08:00
Huang, Tao
05b41faf3f pinctrl: rockchip: better show irq chip name
When call irq_alloc_domain_generic_chips, pass the name of the irq
chip with bank name instead of just rockchip_gpio_irq.
So we can know the irq belong to which gpio by read /proc/interrupts.

cat /proc/interrupts

before:
 56:        435  rockchip_gpio_irq   3 Level     bcmsdh_sdmmc
 58:          0  rockchip_gpio_irq   5 Edge      power
 87:          2  rockchip_gpio_irq   2 Level     fusb302
105:         36  rockchip_gpio_irq  20 Level     gt9xx
106:          0  rockchip_gpio_irq  21 Level     rk808
109:          0  rockchip_gpio_irq  24 Level     fusb302
209:         42  rockchip_gpio_irq  28 Edge      es8316_interrupt

after:
 56:        401     gpio0   3 Level     bcmsdh_sdmmc
 58:          0     gpio0   5 Edge      power
 87:          2     gpio1   2 Level     fusb302
105:         39     gpio1  20 Level     gt9xx
106:          0     gpio1  21 Level     rk808
109:          0     gpio1  24 Level     fusb302
209:         37     gpio4  28 Edge      es8316_interrupt

Change-Id: Iff7afda770e8493dc4c105c1d251aeae0f69f639
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2016-09-22 18:09:49 +08:00
Huang, Tao
8b9c3887dc arm64: configs: update rockchip config by savedefconfig
Change-Id: Ib70a45ed0a7207705ca5cb3609831a93af5510e9
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
2016-09-22 15:08:41 +08:00
Jianhong Chen
00f8ace787 power: rk818-battery: update to v7.1
1. ajust zero algorithm to smooth low power area;
2. set two level speed for finish charging;
3. check divisor to avoid to be zero;
4. add timeout times for finish adc cablibration;
5. fix some logic error and add more debug info.

Change-Id: I248dc6792304b91473af895d549d2f40bcb7a6e2
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
2016-09-21 16:59:24 +08:00