We need to overwrite the default register value to put the PHY into
low power mode in idle state.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I4c788ce04880d6e25d4454e5594882d511b0bc97
This reverts commit 36040e7744.
After commit 5f3de16bb2 ("clk: rockchip: depends on CPU config").
CLK_RK1808 depends on CPU_RK1808 and CLK_RK3308 depends on CPU_RK3308.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I47b539d06980f5fa0b50ac88792f1db9cea3cb5f
When build with rv1126_defconfig:
before:
text data bss dec hex filename
8796 156 4 8956 22fc drivers/soc/rockchip/rockchip_pvtm.o
after:
text data bss dec hex filename
4508 156 4 4668 123c drivers/soc/rockchip/rockchip_pvtm.o
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I8c49713ebc48586aa4f08fb3ec965890c2beb1a2
default FIQ_DEBUGGER for ROCKCHIP_FIQ_DEBUGGER.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I057ced60a847774c6c67f89d9eedb8f8d31d53b4
This reverts commit c75dc801f4.
default FIQ_DEBUGGER for ROCKCHIP_FIQ_DEBUGGER.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I928f061a92d5c8735ffcd05d5b1f40723d3678e3
When build with rv1126_defconfig:
before:
text data bss dec hex filename
18918 34120 8 53046 cf36 drivers/pinctrl/pinctrl-rockchip.o
after:
text data bss dec hex filename
11726 3028 8 14762 39aa drivers/pinctrl/pinctrl-rockchip.o
Change-Id: I09e85d6a05f9bdee1033584bd1573d41d69633bc
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
for current dmc policy, lineflag1 no need to advanced 3ms
RK356X:
lineflag0: will be used by DRM internal driver
lineflag1: will be used by external module link NVR userspace and DMC.
RK3588:
lineflag0: will be used by DRM internal driver and DMC
lineflag1: will be used by external module link NVR userspace.
NVR userspace can use crtc prop: LINE_FLAG1 to update lineflag num.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8a48aead55b59307823ad829ad5ea205d171b24b
VOP always continue fetch display data from fb,
so we don't need do dirtyfb here, and drm_atomic_helper_dirtyfb
do much operation which will lag the fps.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ie96eb711723547a2d80fe60c7898109444747030
HDMI PHY PLL adds 154M and 119M support, while fixing 146.25M
and 85.5M parameters
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I12465d6c025737b80761d83687ec4d93d18b1c51
The warning logs fixed are "GPU activity takes longer than time interval, ...".
This fix is provided as 496f5e3.diff by Zhigang.Yao@arm.com of support_mali.
The original commit message within 496f5e3.diff:
{
From 496f5e37a803266e71cbf7b6eb5871fe2fcd8931 Mon Sep 17 00:00:00 2001
From: Tu Vuong <tu.vuong@arm.com>
Date: Wed, 09 Feb 2022 09:31:20 +0000
Subject: [PATCH] GPUCORE-30123 Fix incorrect dmesg warning for unexpected GPU activities
The DVFS utilisation calculation detects when the GPU has expended more
cycles than expected compared to the actual time passed. This margin was
not sufficient as it didn't take into account the worst-case scenario
where samples are taken TIMER_DEFAULT_VALUE_MS apart.
}
Change-Id: I16bb904fd77006f6ab1e4419e44a9834550e4c07
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
With multi core patch it will be lack of core id at old combo
hardware probe process.
The error log is shown below on device probe:
mpp_vepu2 ff650000.vepu: can not attach device with same id 0
And also kernel crach on mpp library init.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I92ea5fc3575dad9236878235a396d02da7a3fba5
make ARCH=arm64 rockchip_linux_defconfig rk3588_edge.config
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Change-Id: Id7eb2364c0f65e4d3954eb4c7f66d4bfd8acdfcf
For support kernel logo, don't disable phy when phy probe.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I04168e1374104480c1fa611539938f1374967bd7
The userspace transmits private data through request.signal,
vcnt event return it to userspace through vbl.userdata
Change-Id: I8295a3d4fd91430b3b9fac6c5b6b526e1f266f24
Signed-off-by: Ai ShaoXiang <aisx@rock-chips.com>
Add config option to modularize the DP interface support of DRM.
./ksize.sh drivers/gpu/drm/
before ksize: 536734 Bytes
after kszie: 487941 Bytes
save about: 48793 Bytes
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ie2157fad13a71a3099b79085e0de40efe4b4ab34
Some times we only want use some of the module
of rockchip vop driver(et: rkmpp some times only
wat to use rockchip drm gem),
the real vop drivers is not needed to load.
Add a virtual vop driver let the rockchip drm launch.
Enabled by add following to you dts:
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
}
Change-Id: Id6cd14a735eabaf8b4949330d56f77354e50c51c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Here are 2 hdmi phy pll can use for video port dclk.
There are strategies of how to use hdmi phy pll as follow:
1. hdmi phy pll can be used for video port0/1/2 when output
format under 4K@60Hz;
2. When a video port connect both hdmi0 and hdmi1(may also
connect other output interface), it must hold the hdmi0
and hdmi1 phy pll, and other video port can't use it. if
request dclk is under 4K@60Hz, set the video port dlk parent
as hdmi0 phy pll.if hdmi0 or hdmi1 phy pll is used by other
video port, report a error.
3. When a video port(A) connect hdmi0(may also connect other
output interface but not hdmi1), it must hold the hdmi0
phy pll, and other video port can't use it. If both hdmi0
and hdmi1 phy pll is used by other video port, report a error.
If hdmi0 phy pll is used by another video port(B) and hdmi1
phy pll is free, set hdmi1 phy pll as video port(B) dclk parent
and video port(A) hold hdmi0 phy pll. If hdmi0 phy pll is free,
video port(A) hold hdmi0 pll. If video port(A) hold hdmi0 phy
pll and request dclk is under 4k@60Hz, set hdmi0 phy pll as
video port(A) dclk parent.
4. When a video port(A) connect hdmi1(may also connect other
output interface but not hdmi0), it must hold the hdmi1 phy
pll, and other video port can't use it. If both hdmi0 and hdmi1
phy pll is used by other video port, report a error. If hdmi1
phy pll is used by another video port(B) and hdmi0 phy pll is
free, set hdmi0 phy pll as video port(B) dclk parent and video
port(A) hold hdmi1 phy pll. If hdmi1 phy pll is free, video
port(A) hold hdmi1 pll. If video port(A) hold hdmi1 phy pll and
request dclk is under 4k@60Hz, set hdmi1 phy pll as video port(A)
dclk parent.
5. When a video port connect dp(0, 1, or both, may also connect
other output type but not hdmi0 and hdmi1). If the request dclk
is higher than 4K@60Hz or video port id is 2, do nothing. Otherwise
get a free hdmi phy pll as video port dclk parent. If no free hdmi
phy pll can be get, report a error.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: If412cc2418561315be8e2ad82384be085000a957
And fix bug in address calculation in 422p format.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id0d7b3ad786dbec3774835f3a288448fe5107014
Enable CONFIG_VIDEO_FP5510 used for s5k3l6xx which found on
rk3588s tablet rk806 single board
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: If561e1feecf4cf3c7672594edbc156c2bf90533a
Interface functions may call by different threads, which may
access the same value at the same time. So we need add mutex
lock.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I682820c0eb366d514e21cc54f9ab97d5039a0814
gpiod_get_value would take gpio active state into count. So
the default pattern should be like prsnt-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>
to indicate that 1 means no devices. If we need 0 to indicate no devices,
we should use GPIO_ACTIVE_HIGH instead.
Fixes: cca1a93b9e ("PCI: rockchip: dw: Add present IO detect")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic34debabfccdac357c52df427573decc65eea83f
When using user buffer, hardware crypto is used regardless of
whether the data length is greater than 32K.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I3228910def265765e772da1ab4eda3b54d9927cb
Cluster0_PD is a parent power domain for Cluster1/2/3_PD,
it should be power on first and power down last.
use list_for_each_entry_safe_reverse to make sure the
right order.
Fixes: 8684b9914503("drm/rockchip: vop2: power off all vop pd when enter
suspend mode")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I50a5d53de40131d4878b8e1d4a065ce2b96eb2c8
