This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: Idb2d492d2ceba3029d334777c0c784bce4676666
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I4593151b2624d2ccfaf477d36ff1f4d331f2ca91
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: If1fb768aadc89025cccc131441c3aa32045ba382
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I6d958aa57097209165cf32a671f9612752eec4f1
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I382ee237c596e79e29bf6c4b13a4dc6c0c94344f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: Ibe59e24929f89e6124ee0c74195515421625f386
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: I4fd81155cfbd6c257d3a52eda25714e07a4e6abb
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This allows adding fields to clk_init_data without having to explicitly
set those fields in all the drivers.
Fixes: 2071154513 ("ANDROID: GKI: clk: Initialize in stack clk_init_data to 0 in all drivers")
Change-Id: Ibc59e5fa1e6a9b7aff8612b7501e8f0644cd96ca
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
fix following problem when using pingpong mode
rkcif: Bad frame, pp irq:0x20b frmst:0xda900000 size:1600x600
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: Iaf9222d5465a966047c26b7a7518bbc419cd5748
Remove unnecessary initialization process from core as possible, such
as remove some idle process, shorten delay, remove parsing ext_csd,
remove post-delay for power and so on. All these stuffs are enabled
by CONFIG_ROCKCHIP_THUNDER_BOOT.
Change-Id: I0e2326dd79d938eb82c8cfac9db09e34d6c08987
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This patch adds the qurik to use busrt transfers only
for pl330 controller, even for request with a length of 1.
Although, the correct way should be: if the peripheral request
length is 1, the peripheral should use SINGLE request, and then
notify the dmac using SINGLE mode by src/dst_maxburst with 1.
For example, on the Rockchip SoCs, all the peripherals can use
SINGLE or BURST request by setting GRF registers. it is possible
that if these peripheral drivers are used only for Rockchip SoCs.
Unfortunately, it's not, such as dw uart, which is used so widely,
and we can't set src/dst_maxburst according to the SoCs' specific
to compatible with all the other SoCs.
So, for convenience, all the peripherals are set as BURST request
by default on the Rockchip SoCs. even for request with a length of 1.
the current pl330 driver will perform SINGLE transfer if the client's
maxburst is 1, which still should be working according to chapter 2.6.6
of datasheet which describe how DMAC performs SINGLE transfers for
a BURST request. unfortunately, it's broken on the Rockchip SoCs,
which support only matching transfers, such as BURST transfer for
BURST request, SINGLE transfer for SINGLE request.
Finaly, we add the quirk to specify pl330 to use burst transfers only.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I91c295a0854515131fb9a76757fbd85e5c7b0c15
logo-memory-region is used for passing framebuffer
from bootloader, which store kernel logo image data.
Change-Id: I24ba97be5abdbb8a8760861f7460120eef9ff744
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
According to the datasheet of pl330:
Example 2-1 Using DMAGO with the debug instruction registers
1. Create a program for the DMA channel
2. Store the program in a region of system memory
3. Poll the DBGSTATUS Register to ensure that the debug is idle
4. Write to the DBGINST0 Register
5. Write to the DBGINST1 Register
6. Write zero to the DBGCMD Register
so, we should make sure the debug is idle before step 4/5/6, not
only step 6. if not, there maybe a risk that fail to write DBGINST0/1.
Change-Id: I22253cc5d7cbd68f1c641fbef38617dc9a053c48
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Build iep2 driver for rv1126_defconfig by default.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
Change-Id: I048c3de46492134eac06190c8f25e3a5a5c19175
IEP2 is a hardware ip upgrade from IEP, improving deinterlacing
processing perform, but no other post processing functions
for this version.
Change-Id: Id7f58c3f35c0c033aaa4c104a3f98849e1778f94
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
This is a workaround for dmac register write error by
read once before write to make paddr is stable, which
was caused by asynchronous between dmac_aclk and pclk.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I32e03204d6399db4fe4f40479050cc45e04ddb1f
This patch adds property "xhci-warm-reset-on-suspend-quirk"
for rk3399 DWC3 xHC to do a warm port reset for USB3 port
upon PM suspend.
This patch also deletes the unused property:
snps,usb3-warm-reset-on-resume-quirk
Change-Id: I0d50e1c603a3114f6bc5f822334546c6e1668b0e
Signed-off-by: William Wu <william.wu@rock-chips.com>
The RK3399 Type-C PHY requires that it must hold the PIPE
power state in P2 before initializing the PHY. The current
code reset the whole USB3.0 OTG controller in the DWC3
PM suspend/resume to set the PIPE in P2 if the link_state
is RxDetect, and then power on/off the Type-C PHY safely
during PM suspend/resume.
In this case, we assumed that the RxDetect state meant no
USB device connected. But actually, if an USB 1.0/1.1/2.0
device connected, the link is in the RxDetect State too.
So reset the USB controller will cause the USB 1.0/1.1/2.0
device to be reenumerated upon PM resume.
This patch uses xHC warm port reset instead of controller
reset to set the PIPE in P2. It can avoid reseting the USB
1.0/1.1/2.0 device upon PM resume.
Fixes: c9b15ba1eb ("usb: dwc3: core: prevent re-enumeration in host mode")
Change-Id: I4f02f429019771699993358059731f949140eb08
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new property "snps,xhci-warm-reset-on-suspend-quirk"
to do a warm port reset for xHC USB3 port upon suspend if needed.
Change-Id: Id26ab9ecd933f16a491b6fc13c45346459f78109
Signed-off-by: William Wu <william.wu@rock-chips.com>
vcc18_lcd is the power enable pin of dsi panel board, and it
also provides the rst signal of panel through RC circuit.
When we power on and change the pin directly, the rst will not
power down completely, resulting in the probability that the
screen cannot display after reboot.
so fix it.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ifb47ea23a4bd2d9e41fd317d3c7777e158e54dec
AOSP 9f28439ba714 ("fix size of v3 boot header")
Revert 7261bb083a97 ("Check DTB image size for boot image header version 2 and above")
which failed to repack image without dtb.
Change-Id: I591c0c548229e16482352c94651740de3e0e8b76
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from gpll.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia75c3613573f4a6818cbc18668a66736f011c695
If the parent of one clock is cpll and we set it as dummy clock, the
clock will be a orphan clock and the clk provider will register abortively,
as follows.
[ 0.000000] rockchip_clk_of_add_provider: could not register clk provider
The cause of the error:
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
const char *con_id, bool with_orphans)
{
/* This is to allow this function to be chained to others */
if (!hw || IS_ERR(hw))
return (struct clk *) hw;
if (hw->core->orphan && !with_orphans)
return ERR_PTR(-EPROBE_DEFER);
return clk_hw_create_clk(hw, dev_id, con_id);
}
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7053cd4e0a028a1556c774601d5c01578ee5b1ac
There is no reason to limit the performance on the 'NO-FLUSHP' SoCs,
cuz these platforms are just that the 'FLUSHP' instruction is broken.
so, remove the limit to improve the efficiency.
Change-Id: I6a975f48fedcf4a693d093f91294d33724ef5745
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Used by extcon.
Fixes: 513c60a1ba ("extcon: Add named extcon link")
Change-Id: I5e0e5ab18ecd0e967797a3a8fb52c5f283468643
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
