If DWC3 works as peripheral only mode, XHCI HCD will
not be created and added, so we should only get XHCI
HCD in host mode.
Change-Id: Iefb02431d6a973050986963bbabe0a943283f4b3
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Since the commit a2be4bc ('FIXUP: UPSTREAM: phy: Add USB
Type-C PHY driver for rk3399') has created 2 PHY devices
separately for tcphy USB3 and DisplyPort, and registered
them under the child node, we should also add the USB3
and DP child nodes to dts.
Change-Id: Iffe5dc961dc96b2b41476b1db2949e95c275e19f
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch aims to make code sync with upstream[1]. And it
can fix the following issues:
1. Introduce the EXTCON_PROP_USB_SS property to support both
DP 2*lanes + USB3.0 and DP 4*lanes + USB2.0 mode;
2. Fix the bug that the USB3 phy power on should not return
err when no USB attached, since the USB3 controller will
power_on phy at probe/resume, even though there is no USB3
super speed device attached. At this case, return 0 and do
nothing is better.
3. Create 2 PHY devices separately for USB3 and DisplyPort,
and registers them under the child node.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
commit <e96be45cb84e29e58f35ed460a859b61e8bf28c5>
Change-Id: Ib388a072f11d80624ec6e16291eab497a3dcb0e1
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
ID dig disconnect interrupt will happen and notify dwc3 controller
to remove hcd as soon as resume, and release root hub, but the hcd
has not resume, so there is a logic error and it may result in NULL
pointer, this patch forbid remove hcd when the state of hcd is suspend.
Change-Id: Ia5673848a23528cd053d75910c0fdbddf0927a40
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The drm callback ->detect and ->get_modes seems is not power safe,
they may be called when device is power off, do register access on
detect or get_modes will cause system die.
Here is the path call ->detect before analogix_dp power on
[<ffffff800843babc>] analogix_dp_detect+0x44/0xdc
[<ffffff80083fd840>] drm_helper_probe_single_connector_modes_merge_bits+0xe8/0x41c
[<ffffff80083fdb84>] drm_helper_probe_single_connector_modes+0x10/0x18
[<ffffff8008418d24>] drm_mode_getconnector+0xf4/0x304
[<ffffff800840cff0>] drm_ioctl+0x23c/0x390
[<ffffff80081a8adc>] do_vfs_ioctl+0x4b8/0x58c
[<ffffff80081a8c10>] SyS_ioctl+0x60/0x88
Change-Id: Ica3fda1f22f903ee9ba2f0caed40cdae9bdfa32b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9374135)
AFBC is arm vendor format, it's a compressed format.
The AFBC format is supported by rk3399 vop big.
We know little about AFBC layout, hope to some guys can
fixme about the afbc comment.
Change-Id: I9b3edaeb8cc7ffb792820c2f9a60d91fd0c6c28b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9324667/)
enable ROCKCHIP_ANALOGIX_DP, ROCKCHIP_INNO_HDMI and ROCKCHIP_LVDS
Change-Id: I2bd0836bdb04b2c560834e8de31b37ce7a4fae79
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
We make sure that get drvdata dwc before register extcon
notifier and schedule otg_work, so we can remove the dwc
NULL pointer handle safely.
Also, change the WARN_ON to dev_warn, and avoid log noise.
Change-Id: Icececf3bb5ad510b91d2c3a50e2126225673605e
Signed-off-by: William wu <wulf@rock-chips.com>
Use a lock to ensure that the extcon callback only runs after probe()
has finished. In suspend() we unregister the extcon handler to prevent
it from being executed when the controller is suspended, which might
lead to crashes or unexpected behavior.
TEST=build and boot on 3399 board; plug in a USB device and verify
whether it is enumerated; suspend the DUT; resume the DUT; unplug
and re-plug the USB device and verify it is enumerated.
Change-Id: I965e66631a2d0f4d6cc53917d6a6e80bf8774fe1
Signed-off-by: William wu <wulf@rock-chips.com>
We need to ensure the dwc controller stay in P2 state prior
to phy init. In order to set dwc controller in P2 state,
there're two methods:
1. Hold dwc controller in reset while initialize phy.
2. Do OTG reset before phy init, one thing to note here is
that we can't reinit dwc controller again prior to phy init.
We choose the second mothod now. Because asserting the OTG
reset may affect dwc chip operation. The reset will clear all
of the dwc controller registers, and there are no synchronization
primitives, meaning the dwc3 core code could at least in theory
access chip registers while the reset is asserted, with unknown
impact. So we need to deassert the OTG reset as soon as possible.
Since phy init may take a long time, we can't hold the reset while
initialize phy.
Also, we add otg reset if dwc controller works as peripheral mode.
Change-Id: I54fec922308f62bfc7ebdde3e07ede9347e8f70a
Signed-off-by: William wu <wulf@rock-chips.com>
The ARM GICv3 #interrupt-cells need 4 cells to encode an interrupt source.
According to Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt,
the 4th cell is a phandle to a node describing a set of CPUs this interrupt
is affine to. The interrupt must be a PPI, and the node pointed must be a
subnode of the "ppi-partitions" subnode. For interrupt types other than PPI
or PPIs that are not partitionned, this cell must be zero. So we just add
0 for the 4th cell of u2phy1_otg interrupts.
Change-Id: I16ff4e4296064716fe4f7ea35946085e0473f049
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Users of usleep_range() expect that it will _never_ return in less time
than the minimum passed parameter. However, nothing in any of the code
ensures this. Specifically:
usleep_range() => do_usleep_range() => schedule_hrtimeout_range() =>
schedule_hrtimeout_range_clock() just ends up calling schedule() with an
appropriate timeout set using the hrtimer. If someone else happens to
wake up our task then we'll happily return from usleep_range() early.
msleep() already has code to handle this case since it will loop as long
as there was still time left. usleep_range() had no such loop.
The problem is is easily demonstrated with a small bit of test code:
static int usleep_test_task(void *data)
{
atomic_t *done = data;
ktime_t start, end;
start = ktime_get();
usleep_range(50000, 100000);
end = ktime_get();
pr_info("Requested 50000 - 100000 us. Actually slept for %llu us\n",
(unsigned long long)ktime_to_us(ktime_sub(end, start)));
atomic_set(done, 1);
return 0;
}
static void run_usleep_test(void)
{
struct task_struct *t;
atomic_t done;
atomic_set(&done, 0);
t = kthread_run(usleep_test_task, &done, "usleep_test_task");
while (!atomic_read(&done)) {
wake_up_process(t);
udelay(1000);
}
kthread_stop(t);
}
If you run the above code without this patch you get things like:
Requested 50000 - 100000 us. Actually slept for 967 us
If you run the above code _with_ this patch, you get:
Requested 50000 - 100000 us. Actually slept for 50001 us
Presumably this problem was not detected before because:
- It's not terribly common to use wake_up_process() directly.
- Other ways for processes to wake up are not typically mixed with
usleep_range().
- There aren't lots of places that use usleep_range(), since many people
call either msleep() or udelay().
Change-Id: Ibb93ce0dd9fb9688d4a8d10447c098c1dfbd7a1d
Reported-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Andreas Mohr <andim2@users.sf.net>
(am from https://patchwork.kernel.org/patch/9369963/)
This adds support no relinquishing port from ehci to ohci.
Change-Id: I153a85df7407b8e546e75018d71e3763c8f41a10
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add a quirk to cancel relinquishing port from ehci to
abnormal ohci when HS device is not ready connected.
To support this function, the no-relinquish-port property
must be specified in ehci node of dt.
Change-Id: Ief0b24cf9e58dde28f386ea67fe8936e8fd74f2d
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
used to calculate the delay time for change dcdc voltage.
Change-Id: I6bb462ef087b9ce6aa98991a1b961ed5f57bb3c8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Commit 520bd7a8b4 ("mmc: core: Optimize boot time by detecting cards
simultaneously") causes regressions for some platforms.
These platforms relies on fixed mmcblk device indexes, instead of
deploying the defacto standard with UUID/PARTUUID. In other words their
rootfs needs to be available at hardcoded paths, like /dev/mmcblk0p2.
Such guarantees have never been made by the kernel, but clearly the above
commit changes the behaviour. More precisely, because of that the order
changes of how cards becomes detected, so do their corresponding mmcblk
device indexes.
As the above commit significantly improves boot time for some platforms
(magnitude of seconds), let's avoid reverting this change but instead
restore the behaviour of how mmcblk device indexes becomes picked.
By using the same index for the mmcblk device as for the corresponding mmc
host device, the probe order of mmc host devices decides the index we get
for the mmcblk device.
For those platforms that suffers from a regression, one could expect that
this updated behaviour should be sufficient to meet their expectations of
"fixed" mmcblk device indexes.
Another side effect from this change, is that the same index is used for
the mmc host device, the mmcblk device and the mmc block queue. That
should clarify their relationship.
Reported-by: Peter Hurley <peter@hurleysoftware.com>
Reported-by: Laszlo Fiat <laszlo.fiat@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Fixes: 520bd7a8b4 ("mmc: core: Optimize boot time by detecting cards
simultaneously")
Cc: <stable@vger.kernel.org>
Change-Id: I8fe12a3858f3e2ace8fcc785befbae588108e2db
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
(cherry picked from commit 9aaf3437aa)
Practice shows :
The sd cards are easier to be identified after increase delay
Change-Id: I48912e2d184902fab8b27edba70281f0bf19b9ab
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
support delay time in microseconds required to
rise or fall to this new voltage
Change-Id: I8d096500a3dcb376785285d08228961cf6b26ce0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
support delay time in microseconds required to
rise or fall to this new voltage
Change-Id: I1f7c77356e650b9ff01ad0e63fd384e25f774eac
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The meaning of the property value is as below:
The value of the property EXTCON_PROP_USB_SS is 0: USB1.0 or USB2.0
The value of the property EXTCON_PROP_USB_SS is 1: USB3.0
we change the logic of fusb302 notification , if dp sink device is connected, dfp is set to 1,
and use pin assignment value to define if sink device support usb3.0.
Change-Id: Ib7afaf9b754b4585b0ef211dd246059b8ab72904
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
The disvr usb audio sampling rate is through nanoc reported to
the kernel, so don't need the kernel again set the sampling rate.
Change-Id: I60409fc579952a196c4fe40f678e87d505a7508d
Signed-off-by: wjh <wjh@rock-chips.com>
No need notify charging-external-connector state when otg host connect.
Change-Id: I1d5c6e4fb2ad504f169ef0fd5b82b06f31783922
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Some rk3399 board(rk3399 MID or rk3399 VR) is use rk81x generated vbus.
So need fusb302 send a extcon to notify rk818 when OTG or DP cable plugin.
If use EXTCON_USB_HOST, the extcon will notify dwc3 and rk818_charger at
the same time,so need to add a new extcon EXTCON_USB_VBUS_EN.
Change-Id: Ib019ed7c2d4343c50dcef739ab3076f592979ea0
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
No functional change. Rename "enum phy_mode" to
"enum xgene_phy_mode" in xgene phy driver in
preparation for adding set_mode callback in
phy core.
Change-Id: I7e569e1fb82a308e79d30a80323e0c3c338dd68c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Loc Ho <lho@apm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 65048f4dd9)
rk3399-box Type-C0 USB needs to support peripheral mode
and host mode, so we set dr_mode as otg.
Change-Id: If94cdca3ec1d018c3f9aad14bb2c1e15e10e9c51
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The upstream commit 5e8ec28765 (usb: dwc3: gadget: Handle TRB
index 0 when full or empty) only use the HWO = 1 to check if
the TRB ring is full. But refer to DWC3 databook Version 3.00a,
8.2.3.2 TRB Control Bit Rules: When an OUT endpoint receives a
short packet, some TRBs in a chain may still have their HWO bit
set to 1 while belonging to software.
So if HWO=1 and CSP=1 on OUT endpoint, it also means that TRB
ring is empty, software may reclaim those TRBs even though HWO=1.
TEST=use MTP to transfer big data, and then cancel the transition，
check if it can transfer again.
Change-Id: I45cc683dc733ff7a642cfcd3ebc20455ef677753
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The initial use for this is for PHYs that have a mode related to USB OTG.
There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
in the USB PHY to override OTG VBUS and ID signals.
Of course, the enum can be expaned in the future to include modes for
other types of PHYs as well.
Change-Id: Iebc730d7e41c2910fa1be98cbf275d2c73358050
Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 300eb0139c)
Add the new extcon EXTCON_USB_VBUS_EN to enable
vbus output.
Change-Id: I83fb75b2a82ad617dc292967bb4917bbfbcb84cb
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Fix commit 536277d550 ("FROMLIST: extcon: Add the support for
extcon property according to extcon type"), which introduce
EXTCON_PROP_USB_ID property, but upstream don't have such property.
Remove it make merge easy.
Change-Id: I7905049629aa85158b7e705b40018f83fa85a9ac
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
HCI_UART_PROTO_SET flag is set before hci_uart_set_proto call. If we
receive data from tty layer during this procedure, proto pointer may
not be assigned yet, leading to null pointer dereference in rx method
hci_uart_tty_receive.
This patch fixes this issue by introducing HCI_UART_PROTO_READY flag in
order to avoid any proto operation before proto opening and assignment.
Signed-off-by: Loic Poulain <loic.poulain@intel.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
Change-Id: Ibe366f3222cbe7a093cd08aaecbc0de1004088c8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 84cb3df02a)
If enable cabc function, close auto gating, because cabc and auto gating
can't enable at the same time, in addition cabc open and close will lead
to splash screen, so when close cabc, we just set stage up and down to 0.
Change-Id: Ia4561d6adafa956c26d1921caecc7eed97dd218a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
