According to the SI report, SI test items in TP3, which
are not applicable for eDP v1.3 but necessary for eDP
v1.4, can not meet signal requirements.
Add tx_drv_pre_lvl_ctrl, ana_tx_jeq_en, tx_jeq_even_ctrl
and tx_jeq_odd_ctrl to pass above SI test items.
Change-Id: Ie99f009bee7f2a5d459002b22bccca591f298fea
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
drm_fbdev_generic_setup(drm_dev, 0) register fbdev will register drm
client and lead to display black screen after kernel logo, so we
reintroduction rockchip drm fbdev.
fbdev register drm client will show black screen:
drm_kms_helper_hotplug_event
->drm_client_dev_hotplug
->client->funcs->hotplug
->drm_fbdev_client_hotplug
->drm_fb_helper_hotplug_event
->drm_fb_helper_set_par
...
-> drm_atomic_commit
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id2725e26c633c9ef5f4bd01f9f4fa45c072e8ef9
If less this commit, VOP will dead at the system bandwidth
very terrible scene.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie49ea5c3955d98cefbaa360cc8d6ae1a64ca656e
power up plane should be before pd up, otherwise all the
power down module register is zero.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0959d442292e1f3753c965a1a15280cc5de28950
When a NAK is received in one Discover Modes, the Initiator should
skip consuming modes and continue to request Discover Modes for the
rest of SVIDs or register altmodes that have been consumed in
previous ACK.
This fixes a few USB-C Docking Stations failed to register DP
alternate mode since they respond a ACK in the DP SID Discover Modes
first and a NAK in the second VID Discover Modes.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I52d3fae2731fbe88445f47be3ffee20751309ea4
Cluster win only need to attach share_id_prop as ordinary win, just like
esmart parent win.
Fixes: 48c83387b1 ("drm/rockchip: vop2: Add unique share id for Cluster window")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I45a7486c73ca75a04baba6eb1ac4bda3daab3caa
If dts assigned esmart1-win0 as vp1 primary plane but vp1 is disabled,
the esmart1-win0 plane may be lost.
Fixes: 1568e5614d ("drm/rockchip: vop2: not to register crtc for inactive video port")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I13675bd0695c342bceccba224ff64a2e5dc1f9e0
According to Documentation/driver-api/driver-model/driver.rst,
a warning as follow:
-EPROBE_DEFER must not be returned if probe() has already created
child devices, even if those child devices are removed again
in a cleanup path. If -EPROBE_DEFER is returned after a child
device has been registered, it may result in an infinite loop of
.probe() calls to the same driver.
To avoid this issue, we init the audio in .late_register()
of drm_encoder_func.
Change-Id: Id2219e0225a88075780ea4d0d5030b30e4d97f8c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For reboot stress tests, have the below crash.
[ 15.003004] Unable to handle kernel paging request at virtual address ffffffc009c975a0
[ 14.897469] pc : queued_spin_lock_slowpath+0x274/0x420
[ 14.898086] lr : kthread_queue_work+0xb8/0x114
[ 14.899280] sp : ffffffc00cb93c90
[ 14.899280] x29: ffffffc00cb93c90 x28: 0000000000000000 x27: 0000000000000000
[ 14.899284] x26: ffffffc0080bc414 x25: ffffffc0080bc4f0
...
[ 15.010633] CPU: 5 PID: 240 Comm: irq/82-husb311 Tainted: G O 6.1.75 #120
...
[ 15.029917] Call trace:
[ 15.030137] queued_spin_lock_slowpath+0x274/0x420
[ 15.030564] kthread_queue_work+0xb8/0x114
[ 15.030926] tcpm_cc_change+0x60/0xa4
[ 15.031256] tcpci_irq+0x150/0x240
[ 15.031554] husb311_irq+0x50/0x290
[ 15.031863] irq_thread_fn+0x30/0xb0
[ 15.032182] irq_thread+0x16c/0x2c4
[ 15.032490] kthread+0xdc/0xe0
[ 15.032765] ret_from_fork+0x10/0x20
...
This commit addresses the issue by disabling the IRQ before unregistering
the TCPCI port in both the remove and shutdown handlers. This ensures that
no new interrupts are handled after the port is unregistered, preventing
potential race conditions or use-after-free issues.
Fixes: 5e320d0310 ("usb: typec: husb311: set vbus off when shutdown")
Change-Id: Ie2cb85a15f6c63b019e4a000ba65205bc508e483
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This adds 24/26 MHz reference clock frequency setting for
rk3576 soc with SNPS USB2 PHY IP.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I712ab4cb630db9a0cccb4174ce59ef6dbafe2df0
Writing reg 0x300 BIT(31) may cause the DMA module to falsely
trigger writing data. It will case enc err.
So we need to disable the core clock before writing reg 0x300,
and re-enable the core clock after writing reg 0x300.
Change-Id: Ib385b3aa120533cd42b70b548120d219ceaf4fb5
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
The original on/off hdcp process will cause hdmi and vop to be on/off,
which will affect other display interfaces in the mirror scenario.
Change-Id: I1f83063e800beb0b78cd793971e5f4f65b8bf55e
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The parent clock of PCLK_HDPTX_APB is PCLK_PMUPHY_ROOT,
which must be always on.
In order to reduce power consumption, replace apb clock
PCLK_PMUPHY_ROOT by controllable PCLK_HDPTX_APB in
suspending and resuming.
Change-Id: I1103b9bf542bacfd021de9a2553265fd6960e6d5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This patch supports select and swap ADC data, the item
'Left Right' is default.
For example, swap left and right for ADC:
----
amixer -c 0 sset 'ADC Data Select' 'Right Left'
Simple mixer control 'ADC Data Select',0
Capabilities: enum
Items: 'Left Right' 'Left Left' 'Right Right' 'Right Left'
Item0: 'Right Left'
Change-Id: Ied9296929010e93773cf335f210c3ec7be12481e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
For RK3576 VP0 enable ACM[set acm bypass from 1 to 0] must at standby mode, otherwise
will lead to timing error, so we enable ACM by default.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7711cd0ca5b56c3a7bfef800bf9e61a5c0697e90
Generally speaking, the codec needs to ensure the normal
input of left and right channels independently. If you
want to forcethe duplication of channels, you can configure
it through the control node in the user layer.
Enabling ALC NG here will cause the sound pickup effect
to be unstable.
And, the default public version does not need to turn on
the ALC NG function, so as not to introduce non-linear
processing to the backend algorithm and cause unnecessary
confusion to developers.
Change-Id: I52e376c7d992d4bd08e863134b4c596cbfccbe2b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
ciu clock from CRU is 2 times of interface clock, so the delay number
maybe not so accurate as the sample phase is based on interface clock.
Change-Id: Ib8d66f1c7af18fa3888dafc4528a95aabfa8572f
Fixes: 1505eda5b9 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
The parent clock of PCLK_HDPTX_APB is PCLK_PMUPHY_ROOT,
which must be always on.
In order to reduce power consumption, replace apb clock
PCLK_PMUPHY_ROOT by controllable PCLK_HDPTX_APB in
suspend and plug out.
Change-Id: I856fa05382ea50a7541195d49941c113bbe3986a
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
