ARM CPUs with speculative prefetching have undefined behaviors when the
same physical page is mapped to two different virtual addresses with
conflicting cache attributes.
since many recent systems include IOMMU functionality (i.e., remapping
of discontiguous physical pages into a virtually-contiguous address
range for I/O devices), it is desirable to support allocating any
available OS memory for use by the I/O devices. however, since many
systems do not support cache coherency between the CPU and DMA devices,
these devices are left with using DMA-coherent allocations from the OS
(which severely limits the benefit of an IOMMU) or performing cache
maintenance (which can be a severe performance loss, particularly on
systems with outer caches, compared to using DMA-coherent memory).
this change adds an API for allocating pages from the OS with specific
cache maintenance properties and ensures that the kernel's mapping
of the page reflects the desired cache attributes, in line with the
ARMv7 architectural requirements
Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0
Signed-off-by: Gary King <gking@nvidia.com>
add a kernel configuration to map the kernel's lowmem pages using PTE
mappings, rather than the default behavior of 1MiB section mappings.
on ARMv7 processors, to support allocating pages with DMA-coherent
cache attributes, the cache attributes specified in the kernel's
mapping must match cache attributes specified for other mappings;
to ensure that this is the case, the kernel's attributes must be
specified on a per-page basis.
to avoid problems caused by the init_mm page table allocations exceeding
the available initial memory, when this config is enabled lowmem is
initially mapped using sections (matches current behavior), then remapped
using pages after bootmem is initialized
Change-Id: I8a6feba1d6806d007e17d9d4616525b0446c0fb1
Signed-off-by: Gary King <gking@nvidia.com>
Added an ioctl to set the bit format for I2S between "DSP"/"PCM" mode and
normal mode (set by board file)
Signed-off-by: Iliyan Malchev <malchev@google.com>
-- creates /dev/spdif_out and /dev/spdif_out_ctl for playback and control
settings.
-- playback only
Change-Id: I19af1d41e13dedef650784835339ef9718300d0c
Signed-off-by: Iliyan Malchev <malchev@google.com>
This patch replaces the error counter with two separate error counters, one for
late dma callbacks, and another for overruns (during recording) or underruns
(during playback). The ioctls TEGRA_AUDIO_IN_GET_ERROR_COUNT and
TEGRA_AUDIO_OUT_GET_ERROR_COUNT now take a pointer to a struct containing both
error counters.
Signed-off-by: Iliyan Malchev <malchev@google.com>
Add a new 'reset' clk op. This can be provided for any clock,
not just peripherals.
Change-Id: I0742cfad1587ddc006066c7fa9bc22f180c04e6f
Signed-off-by: Dima Zavin <dima@android.com>
nvmap and nvhost will behave improperly if iovmm is not present when
their respective devices are probed; however, the probe ordering depends
on the order the initcalls are made to register the drivers. move
iovmm-gart into subsys_initcall to ensure that it is registered earlier
than other drivers
Change-Id: If3e07ce239e593a0833a3381cd1132f5d6ef6786
Signed-off-by: Gary King <gking@nvidia.com>
The OTG driver disables the gadget device when the cable is
removed, so there is no need to check if the cable is plugged
before touching registers.
Change-Id: I0b1a3a8b07560d3eca2e2e25574b5219e3373808
Signed-off-by: Benoit Goby <benoit@android.com>
On suspend, dr_controller_stop disable interrupts and on resume, interrupts
are disabled until dr_controller_run is called, so it is safe to call
fsl_udc_clk_suspend/resume with interrupts and the spinlock unlocked.
Change-Id: I33618295ea096a4bfd796d1a07dfc9722e7786b0
Signed-off-by: Benoit Goby <benoit@android.com>
The upstream DC needs to be clocked for accesses to HDMI to not hard lock the
system. Because we don't know if HDMI is conencted to disp1 or disp2 we need
to enable both until we set the DC mux.
Change-Id: Iab7df9911aa9034ea559896850787e4eff3237d7
Signed-off-by: Erik Gilling <konkers@android.com>
configure the PMC interrupt polarity low, and register IRQ
numbers with the TPS6586X core and RTC
Change-Id: Iba08704bd1355ed00af3d9132118ce095c5118fe
Signed-off-by: Gary King <gking@nvidia.com>
Save/restore SLINK_COMMAND_0 register.
Wait for in-progress transactions to complete before suspend.
Reject and WARN_ON transactions when suspended.
Change-Id: I0527781f0bf95781afa3a35a68282cde2f0189ae
Signed-off-by: Todd Poynor <toddpoynor@google.com>
