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Author SHA1 Message Date
Leo Yan
60fa5196c8 UPSTREAM: coresight: etm-perf: Clarify comment on perf options 
In theory, the options should be arbitrary values and are neutral for
any ETM version; so far perf tool uses ETMv3.5/PTM ETMCR config bits
except for register's bit definitions, also uses as options.

This can introduce confusion, especially if we want to add a new option
but the new option is not supported by ETMv3.5/PTM ETMCR.  But on the
other hand, we cannot change options since these options are generic
CoreSight PMU ABI.

For easier maintenance and avoid confusion, this patch refines the
comment to clarify perf options, and gives out the background info for
these bits are coming from ETMv3.5/PTM.  Afterwards, we should take
these options as general knobs, and if there have any confliction with
ETMv3.5/PTM, should consider to define saperate macros for ETMv3.5/PTM
ETMCR config bits.

Bug: 174685394
Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210206150833.42120-2-leo.yan@linaro.org
Link: https://lore.kernel.org/r/20210211172038.2483517-2-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 53abf3fe83)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I39e8f7f4e2e46d91b54633d109a5f6b6ce44754c
 2021-03-01 12:52:12 -08:00
Uwe Kleine-König
c15968e1d6 UPSTREAM: coresight: etm4x: Fix merge resolution for amba rework 
This was non-trivial to get right because commits
c23bc382ef ("coresight: etm4x: Refactor probing routine") and
5214b56358 ("coresight: etm4x: Add support for sysreg only devices")
changed the code flow considerably. With this change the driver can be
built again.

Bug: 174685394
Fixes: 0573d3fa48 ("Merge branch 'devel-stable' of git://git.armlinux.org.uk/~rmk/linux-arm into char-misc-next")
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Link: https://lore.kernel.org/r/20210205130848.20009-1-uwe@kleine-koenig.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 1609faa9e6)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ifbd89b1e5015793e951a1cafd6c7ebdf345c0389
 2021-03-01 12:52:12 -08:00
Suzuki K Poulose
c68c8910e8 UPSTREAM: coresight: etm4x: Handle accesses to TRCSTALLCTLR 
TRCSTALLCTLR register is only implemented if

   TRCIDR3.STALLCTL == 0b1

Make sure the driver touches the register only it is implemented.

Bug: 174685394
Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com
Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-32-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit f728960633)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I9f8fb2fa937246e3380f31676c67be7a76cc1d15
 2021-03-01 12:52:12 -08:00
Jonathan Zhou
5770a56a55 UPSTREAM: coresight: Add support for v8.4 SelfHosted tracing 
v8.4 tracing extensions added support for trace filtering controlled
by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
tracing if we are running the kernel at EL2.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ Move the trace filtering setup etm_init_arch_data() and clean ups]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-31-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit e5d51fbe9b)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ice274286e52c2d0f0b13485ff1ba0de82956e70d
 2021-03-01 12:52:12 -08:00
Jonathan Zhou
91fd5fe63a UPSTREAM: arm64: Add TRFCR_ELx definitions 
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.

[ split the register definitions to separate patch
  rename some of the symbols ]

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-30-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4b6929f50d)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I1feeec0c65cb8d7a6c31660dabca479d03102886
 2021-03-01 12:52:12 -08:00
Suzuki K Poulose
b122b1ed1c UPSTREAM: dts: bindings: coresight: ETM system register access only units 
Document the bindings for ETMs with system register accesses.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-27-suzuki.poulose@arm.com
Cc: devicetree@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-29-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 61c68c68b8)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I8f62b0c38d004112a1be5c37d59d3c88ee7b2649
 2021-03-01 12:52:11 -08:00
Suzuki K Poulose
0a8343aced UPSTREAM: coresight: etm4x: Add support for sysreg only devices 
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices. System register access is not permitted to
TRCPDCR and thus skip access to them.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-28-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 5214b56358)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I7918a1490a987c87638467419d9925241fd91bd1
 2021-03-01 12:52:11 -08:00
Suzuki K Poulose
924bda3def UPSTREAM: coresight: etm4x: Run arch feature detection on the CPU 
As we are about to add support for system register based devices,
we don't get an AMBA pid. So, the detection code could check
the system registers running on the CPU to check for the architecture
specific features. Thus we move the arch feature detection to
run on the CPU. We cannot always read the PID from the HW, as the
PID could be overridden by DT for broken devices. So, use the
PID from AMBA layer if available.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-25-suzuki.poulose@arm.com
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: liuqi115@huawei.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-27-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit e97db2cf09)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I6872de0c7a4457853f02cfae175ede1cf8ef3cf3
 2021-03-01 12:52:11 -08:00
Suzuki K Poulose
e293a5c64d UPSTREAM: coresight: etm4x: Refactor probing routine 
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-26-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit c23bc382ef)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I2c84d40d64d829dcba6b1a2b896742b58feccb6c
 2021-03-01 12:52:11 -08:00
Suzuki K Poulose
059c93dd18 UPSTREAM: coresight: etm4x: Detect system instructions support 
ETM v4.4 onwards adds support for system instruction access
to the ETM. Detect the support on an ETM and switch to using the
mode when available.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-25-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit dc1747a716)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ib121738020a2a5e0ec5aaf41053fd4915d82cb18
 2021-03-01 12:52:11 -08:00
Suzuki K Poulose
7b2b89a818 UPSTREAM: coresight: etm4x: Add necessary synchronization for sysreg access 
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-24-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 1ab3bb9df5)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I21eac5abfc4a683a121208b9de7e1934fcf7c8d0
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
f0675f6596 UPSTREAM: coresight: etm4x: Expose trcdevarch via sysfs 
Expose the TRCDEVARCH register via the sysfs for component
detection. Given that the TRCIDR1 may not completely identify
the ETM component and instead need to use TRCDEVARCH, expose
this via sysfs for tools to use it for identification.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-21-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-23-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4211bfce1e)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Id2647488d3a74e235899ea1e7fe2a02474524188
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
af6455f4f8 UPSTREAM: coresight: etm4x: Use TRCDEVARCH for component discovery 
We have been using TRCIDR1 for detecting the ETM version. This
is in preparation for the future IP support.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-22-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 8b94db1eda)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I872093ed421325820de275a100c4c2b182078247
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
43001f71c7 UPSTREAM: coresight: etm4x: Detect access early on the target CPU 
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-21-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit fd6e790500)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: If8c9ee0401053918558d4f4c46e0262d1a7e8a47
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
5dcbcc2873 UPSTREAM: coresight: etm4x: Handle ETM architecture version 
We are about to rely on TRCDEVARCH for detecting the ETM
and its architecture version, falling back to TRCIDR1 if
the former is not implemented (in older broken implementations).

Also, we use the architecture version information to
make some decisions. Streamline the architecture version
handling by adding helpers.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-20-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit e49516e2df)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I2b0ef0d0b9ff4849446129aa224a33dc8f0d2004
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
263f3f5ac7 UPSTREAM: coresight: etm4x: Clean up exception level masks 
etm4_get_access_type() calculates the exception level bits
for use in address comparator registers. This is also used
by the TRCVICTLR register by shifting to the required position.

This patch cleans up the logic to make etm4_get_access_type()
calculate a generic mask which can be used by all users by
shifting to their field.

No functional changes intended.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-17-suzuki.poulose@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-19-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4d1b1fd729)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Idc8851039a9b12ee56046deeef2b463084b75da4
 2021-03-01 12:52:10 -08:00
Suzuki K Poulose
93b3b6d6bd UPSTREAM: coresight: etm4x: Cleanup secure exception level masks 
We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-18-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 1d3eead7e9)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I56f12ada86b4106ff561573945b2c8e692a9de3e
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
2280659fca UPSTREAM: coresight: etm4x: Check for Software Lock 
The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-17-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 33d5573a15)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Iff3ee426620194468c88fd395b5ca97c83d4f25c
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
145b2c9b14 UPSTREAM: coresight: etm4x: Define DEVARCH register fields 
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-16-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit d02dfac343)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I7f062ad0a0f87cb4808d38dc92d927361d2324d5
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
7882f86670 UPSTREAM: coresight: etm4x: Hide sysfs attributes for unavailable registers 
Some of the management registers in ETMv4.x are not accessible
via system register instructions. Thus we must hide the sysfs
files exposing them to the userspace, to prevent system crashes.

This patch adds an is_visible() routine to control the visibility
at runtime for the registers that may not be accessed.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-13-suzuki.poulose@arm.com
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-15-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 91b9f01854)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I0846bafe4ea1b1031d6ab2532fbdf6e1edbf259a
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
c20520513e UPSTREAM: coresight: etm4x: Add sysreg access helpers 
ETM architecture defines the system instructions for accessing
via register accesses. Add basic support for accessing a given
register via system instructions.

We split the list of registers as :
 1) Accessible only from memory mapped interface
 2) Accessible from system register instructions.

All registers are accessible via the memory-mapped interface.
However, some registers are not accessible via the system
instructions. This list is then used to further filter out
the files we expose via sysfs.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-12-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-14-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 03336d0f4d)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ie6fcd244b8187e0d34bcb60fccc6cfedf82d271f
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
4d82ff1eb6 UPSTREAM: coresight: etm4x: Add commentary on the registers 
As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-11-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-13-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4f2a67266a)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I446a7e25dcbdedab0e6ae2a7e56cd4dc50b0efb1
 2021-03-01 12:52:09 -08:00
Suzuki K Poulose
8ae6d897c0 UPSTREAM: coresight: etm4x: Make offset available for sysfs attributes 
Some of the ETM management registers are not accessible via
system instructions. Thus we need to filter accesses to these
registers depending on the access mechanism for the ETM at runtime.
The driver can cope with this for normal operation, by regular
checks. But the driver also exposes them via sysfs, which now
needs to be removed.

So far, we have used the generic coresight sysfs helper macros
to export a given device register, defining a "show" operation
per register. This is not helpful to filter the files at runtime,
based on the access.

In order to do this dynamically, we need to filter the attributes
by offsets and hard coded "show" functions doesn't make this easy.
Thus, switch to extended attributes, storing the offset in the scratch
space. This allows us to implement filtering based on the offset and
also saves us some text size. This will be later used for determining
a given attribute must be "visible" via sysfs.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-10-suzuki.poulose@arm.com
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-12-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit c03ceec116)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I970e464e881b1d6eda10b2bfb49c0750668374e8
 2021-03-01 12:52:08 -08:00
Suzuki K Poulose
bba030bcee UPSTREAM: coresight: etm4x: Convert all register accesses 
Convert all register accesses from etm4x driver to use a wrapper
to allow switching the access at runtime with little overhead.

co-developed by sed tool ;-), mostly equivalent to :

s/readl\(_relaxed\)\?(drvdata->base + \(.*\))/etm4x_\1_read32(csdev, \2)
s/writel\(_relaxed\)\?(\(.*\), drvdata->base + \(.*\))/etm4x_\1_write32(csdev, \2, \3)

We don't want to replace them with the csdev_access_* to
avoid a function call for every register access for system
register access. This is a prepartory step to add system
register access later where the support is available.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-9-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-11-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit f5bd523690)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I2b961597fca826b4d608c417869b820828941cb9
 2021-03-01 12:52:08 -08:00
Suzuki K Poulose
d3a24f5c62 UPSTREAM: coresight: etm4x: Always read the registers on the host CPU 
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-10-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 5e2acf9d5d)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I5b06467bbc1011cb4ab84c25712a4647f803c16a
 2021-03-01 12:52:08 -08:00
Suzuki K Poulose
39bf277b23 UPSTREAM: coresight: Convert claim/disclaim operations to use access wrappers 
Convert the generic CLAIM tag management APIs to use the
device access layer abstraction.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-7-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-9-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 8ce0029658)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I9bd5d35e5fa3b11531bce45b47efc28f99d49f83
 2021-03-01 12:52:08 -08:00
Suzuki K Poulose
0c890c3fdf UPSTREAM: coresight: Convert coresight_timeout to use access abstraction 
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-6-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-8-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 020052825e)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I501cb5db6842c365813390e3bfc75231e43d04a5
 2021-03-01 12:52:08 -08:00
Suzuki K Poulose
37b6c2ad00 UPSTREAM: coresight: tpiu: Prepare for using coresight device access abstraction 
Prepare the TPIU driver to make use of the CoreSight device access
abstraction layer. The driver touches the device even before the
coresight device is registered. Thus we could be accessing the
devices without a csdev. As we are about to use the abstraction
layer for accessing the device, pass in the access directly
to avoid having to deal with the un-initialised csdev.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-5-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-7-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4eb1d85cfd)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ia1075ed59dc9b1cceb778786c5892e377d737495
 2021-03-01 12:52:07 -08:00
Suzuki K Poulose
a74e3236dd UPSTREAM: coresight: Introduce device access abstraction 
We are about to introduce support for sysreg access to ETMv4.4+
component. Since there are generic routines that access the
registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout)
and in order to preserve the logic of these operations at a
single place we introduce an abstraction layer for the accesses
to a given device.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-4-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-6-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 6e736c60a9)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ie1e48d480cb73155797f7c335db603078ac32fdf
 2021-03-01 12:52:07 -08:00
Suzuki K Poulose
c7a868d7a7 UPSTREAM: coresight: etm4x: Skip accessing TRCPDCR in save/restore 
When the ETM is affected by Qualcomm errata, modifying the
TRCPDCR could cause the system hang. Even though this is
taken care of during enable/disable ETM, the ETM state
save/restore could still access the TRCPDCR. Make sure
we skip the access during the save/restore.

Found by code inspection.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-3-suzuki.poulose@arm.com
Fixes: 02510a5aa7 ("coresight: etm4x: Add support to skip trace unit power up")
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Tingwei Zhang <tingwei@codeaurora.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-5-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit df81b43802)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ie4a3671f4a8430e410f0de00279a3a17dfc3b8fc
 2021-03-01 12:52:07 -08:00
Suzuki K Poulose
ec20e345e0 UPSTREAM: coresight: etm4x: Handle access to TRCSSPCICRn 
TRCSSPCICR<n> is present only if all of the following are true:
	TRCIDR4.NUMSSCC > n.
	TRCIDR4.NUMPC > 0b0000 .
	TRCSSCSR<n>.PC == 0b1

Add a helper function to check all the conditions.

Bug: 174685394
Link: https://lore.kernel.org/r/20210110224850.1880240-2-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-4-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit f6a18f354c)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I3a0a934be80b7efc4ebc17ccaee5eae35be56b2a
 2021-03-01 12:52:07 -08:00
Chunyan Zhang
0134ee2350 UPSTREAM: coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 
Add AMBA UCI id to support Cortex-A55(Ananke) and Cortex-A75(Promethus).

Reviewed by: Mike Leach <mike.leach@linaro.org>

Bug: 174685394
Link: https://lore.kernel.org/r/20210118065549.197489-1-zhang.lyra@gmail.com
Signed-off-by: Bin Ji <bin.ji@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-3-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit b8336ad947)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ic6ae4beb525eb856254f026ea3d43b6e3422e2f3
 2021-03-01 12:52:07 -08:00
Markus Elfring
fa9017b8d1 UPSTREAM: coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() 
A local variable was used only within an else branch.
Thus move the definition for the variable “cs_fwnode” into
the corresponding code block.

This issue was detected by using the Coccinelle software.

Bug: 174685394
Link: https://lore.kernel.org/r/c1b09b27-9012-324f-28d0-ba820dc468a5@web.de
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-2-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 65b2728145)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I391ddd6f04314732b3391fe07dcba5d90383b5f1
 2021-03-01 12:52:07 -08:00
Uwe Kleine-König
ebe992a1ea BACKPORT: UPSTREAM: amba: Make the remove callback return void 
All amba drivers return 0 in their remove callback. Together with the
driver core ignoring the return value anyhow, it doesn't make sense to
return a value here.

Change the remove prototype to return void, which makes it explicit that
returning an error value doesn't work as expected. This simplifies changing
the core remove callback to return void, too.

Bug: 174685394
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org> # for drivers/memory
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> # for hwtracing/coresight
Acked-By: Vinod Koul <vkoul@kernel.org> # for dmaengine
Acked-by: Guenter Roeck <linux@roeck-us.net> # for watchdog
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Takashi Iwai <tiwai@suse.de> # for sound
Acked-by: Vladimir Zapolskiy <vz@mleia.com> # for memory/pl172
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20210126165835.687514-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
(cherry picked from commit 3fd269e74f)
[Fixed conflicts in:
 - drivers/amba/bus.c
 - drivers/vfio/platform/vfio_amba.c
 by just removing the return value keeping the code as-is in android]
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: Ia0ddc88b7d47bb94ae34a168b48c08eb7f95f7e4
 2021-03-01 12:52:06 -08:00
Qi Liu
ff559faca0 UPSTREAM: coresight: etm4x: Modify core-commit to avoid HiSilicon ETM overflow 
The ETM device can't keep up with the core pipeline when cpu core
is at full speed. This may cause overflow within core and its ETM.
This is a common phenomenon on ETM devices.

On HiSilicon Hip08 platform, a specific feature is added to set
core pipeline. So commit rate can be reduced manually to avoid ETM
overflow.

Bug: 174685394
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
[Modified changelog title and Kconfig description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit e72550928f)
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I871af35685ae02a04fee437d514bc05a49c63e56
 2021-03-01 12:52:06 -08:00
Subash Abhinov Kasiviswanathan
0e4a34d08e ANDROID: GKI: Enable CONFIG_NETFILTER_XT_TARGET_TEE=y 
This is needed to redirect packets from one interface to another.

Bug: 181230766
Change-Id: I0c74c69906246a98d24951e959e59d771caa6046
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
 2021-03-01 20:19:57 +00:00
Sudarshan Rajagopalan
94cf23d88a ANDROID: GKI: Update abi_gki_aarch64_qcom for zram and zsmalloc 
Update abi_gki_aarch64_qcom to include symbols used by
zram and zsmalloc modules.

Bug: 180997582
Change-Id: I1427696610c64f99351350929da315724594b054
Signed-off-by: Sudarshan Rajagopalan <sudaraja@codeaurora.org>
Signed-off-by: Chris Goldsworthy <cgoldswo@codeaurora.org>
 2021-03-01 19:48:30 +00:00
J. Avila
bb41438152 ANDROID: sched/rt: Only enable RT sync for SMP targets 
The rt sync wakeup support has a condition which relies on a field that
exists only when CONFIG_SMP is defined, causing a compilation issue.
Since sync wakeup has no real meaning on a non-SMP system, we can just
drop the CONFIG_RT_GROUP_SCHED part of the #ifdef.

Fixes: da5f3cd378 ("ANDROID: sched/rt: Add support for rt sync wakeups")
Signed-off-by: J. Avila <elavila@google.com>
Change-Id: I9b95304408d323b0c1017bd33746ecfbb2b35808
 2021-03-01 18:50:27 +00:00
Marco Elver
88b1f81f40 UPSTREAM: kfence: report sensitive information based on no_hash_pointers 
We cannot rely on CONFIG_DEBUG_KERNEL to decide if we're running a "debug
kernel" where we can safely show potentially sensitive information in the
kernel log.

Instead, simply rely on the newly introduced "no_hash_pointers" to print
unhashed kernel pointers, as well as decide if our reports can include
other potentially sensitive information such as registers and corrupted
bytes.

Link: https://lkml.kernel.org/r/20210223082043.1972742-1-elver@google.com
Signed-off-by: Marco Elver <elver@google.com>
Cc: Timur Tabi <timur@kernel.org>
Cc: Alexander Potapenko <glider@google.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Andrey Konovalov <andreyknvl@google.com>
Cc: Jann Horn <jannh@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Bug: 180086542
Bug: 177201604
(cherry picked from commit 35beccf092)
Signed-off-by: Alexander Potapenko <glider@google.com>
Change-Id: Ia4c74d7525e282d53ac123fa88febeaeff7a316d
 2021-03-01 18:11:05 +01:00
Yurii Zubrytskyi
de43680982 ANDROID: Incremental fs: set the correct access to mapped files 
Backing file needs to have write permissions for all users
even though the mounted view doesn't - otherwise incfs can't
change the internal file data.

Bug: 180535478
Test: adb install <apk>
Signed-off-by: Yurii Zubrytskyi <zyy@google.com>
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I5d7915b28072cff1508ba45b56e844cb678ca466
 2021-03-01 16:16:08 +00:00
Paul Lawrence
0b62157672 ANDROID: Incremental fs: Build merkle tree when enabling verity 
For incfs files that were created without a merkle tree, enabling verity
requires building a merkle tree first. Although this is the same logic
as verity performs, it is not that easy to reconcile the two given that
incfs has the merkle tree potentially when verity is not enabled.

Bug: 160634504
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>

Change-Id: Ia15a4051fa3362820846d65859e3af76b77f8cc4
 2021-03-01 16:16:01 +00:00
Paul Lawrence
850059da54 ANDROID: Incremental fs: Add FS_IOC_MEASURE_VERITY 
Add ioctl to return the verity file digest, compatible with the identical
ioctl in fs/verity/.

Bug: 160634504
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I1bc2dc975b9be122e1c831a25a1d44f27a360f3c
 2021-03-01 16:15:54 +00:00
Paul Lawrence
c630401723 ANDROID: Incremental fs: Store fs-verity state in backing file 
Now fsverity state is preserved across inode eviction.

Added incfs.verity xattr to track when a file is fs-verity enabled.

Bug: 160634504
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I41d90abd55527884d9eff642c9834ad837ff6918
 2021-03-01 16:15:46 +00:00
Paul Lawrence
cf76ed2f0c ANDROID: Incremental fs: Add FS_IOC_GETFLAGS 
Add FS_IOC_GETFLAGS ioctl to incfs. Currently this will only get the
S_VERITY flag.

Bug: 160634504
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: Id79add0db0d66f604ca0f222fe5faec91450ade5
 2021-03-01 16:15:39 +00:00
Paul Lawrence
5bb92dffc9 ANDROID: Incremental fs: Add FS_IOC_ENABLE_VERITY 
Add FS_IOC_ENABLE_VERITY ioctl

When called, calculate measurement, validate signature against fsverity,
and set S_VERITY flag.

This does not (yet) preserve the verity status once the inode is
evicted.

Bug: 160634504
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I88af2721f650098accc72a64528c7d85b753c7f6
 2021-03-01 16:15:32 +00:00
Paul Lawrence
0a1e2d3381 ANDROID: fs-verity: Export function to check signatures 
Allows a file system to provide its own fs-verity implementation
but still to hook into the signature check and control file from
fs-verity

Bug: 160634504
Bug: 170978993
Test: incfs_test running on this + subsequent changes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I02020af460d62fa5eb459a083419208e175005e8
 2021-03-01 16:15:25 +00:00
Paul Lawrence
695e0c5423 ANDROID: Incremental fs: Fix memory leak on closing file 
Bug: 179271514
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: Idc42d02b1df5ac84bdd04e728bfcca5f4cc5d07b
 2021-03-01 16:15:18 +00:00
Paul Lawrence
400d6734bb ANDROID: Incremental fs: inotify on create mapped file 
Bug: 175323815
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: I670e8a7f4a68012d68718a431be3450646a614c0
 2021-03-01 16:15:11 +00:00
Paul Lawrence
a699d0a2ab ANDROID: Incremental fs: inotify support 
Bug: 175323815
Test: incfs_test passes
Signed-off-by: Paul Lawrence <paullawrence@google.com>
Change-Id: Ife372fa2f10dd51f61def9feb461e965d276c6bf
 2021-03-01 16:15:03 +00:00
Kim Low
c3bf09a68b ANDROID: GKI: enable hid-playstation FF 
To enable DualSense rumble, we need to set CONFIG_PLAYSTATION_FF to
"y".

Bug: 167947264
Signed-off-by: Kim Low <kim-huei.low@sony.com>
Change-Id: I88d6187e6b8ca57f291753c6c665feb0380f74c5
 2021-02-28 00:22:53 +00:00