In addition, adjust the initialization order of struct
rockchip_pwm_wave_config members to correspond with their
declaration order within the struct.
Change-Id: I869f1a670f23f726b2fd983af364d3bdd6a9f321
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The driver itself has implemented DMA buffer, and does not require
the map/unmap behavior of the spi framework.
Change-Id: I00abd65233bf5b3112337c8da623bc8afe586bb6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In wave generator mode, the clk_src is used as dclk to generate the
wave, and the mem_clk_src is used to write/read the wave table.
Change-Id: I7d1948a5bb11715ac632c424ef01d6022d15899b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
XT26G12DWSIGA, XT26Q12DWSIGA, XT26G11DWSIGA, XT26Q14DWSIGA.
Change-Id: I733172ed78a95f4d2129c98c9d2c6b92525bde4c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In order to avoid unnecessary interrupt handing behaviors, disable the
interrupt for the wave generator.
Change-Id: Ib397c9814775ca968b77c435db57a5b1ed5df7c6
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If the pc->clk_rate is the same as config->clk_rate, the scaler should
be set to 0. However, using the previous calculation method, the result
would incorrectly be 1.
Fixes: 1504b8ffcf ("pwm: rockchip: add dclk scale config for wave generator mode")
Change-Id: I876f7f530ab841b485b8d7f139adcf825955a160
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The analogix_dp_is_enhanced_mode_available() can be replaced by drm
helper function drm_dp_enhanced_frame_cap().
Change-Id: I18d6faba78c92832d0087b42139e73c9190cbfd3
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
To prevent responding to pending interrupts during initialization.
Soft reset must precede interrupt registration.
Change-Id: I265c52fd509cb0935ca218ed43bbee84e7881d94
Signed-off-by: Simon Xue <xxm@rock-chips.com>
At MOS environment, the irq handle may be triggered immediately
after request irq, the irq handle maybe access vop2 memory, e.g.,
vop3_vp_isr() -> vop2_wb_handler() access vop2->wb->regs, so move
devm_request_irq() to the end of this function to make sure vop2 is
initialized.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3df1cc08069ffcffefa91a523db75fb67cd47de3
This reverts commit 0cbdc8c1da.
The legacy glue layer driver dwc3-rockchip-inno.c is only
used for RK3328/RK3228H platforms, and now they use the
dwc3 core driver instead of the legacy driver, so let's
discard the legacy driver.
Change-Id: Ib1f43aacddea0e0155aa75b0efb58452b0514860
Signed-off-by: William Wu <william.wu@rock-chips.com>
The requirements of rk3506 codec are mainly divided into three
sampling rate groups: 48/44.1/32kHz.
And, the rk3506 codec has internal frequency division, the driver
limits these three mclk inputs:
#define MCLK_REFERENCE_8000 32768000
#define MCLK_REFERENCE_11025 45158400
#define MCLK_REFERENCE_12000 49152000
Therefore, it is necessary to add the "rockchip,mclk-no-set" property
to the SAI4 to avoid switching the mclk frequency in the function of
rockchip_sai_set_sysclk() after the codec configures mclk, causing
the codec filter to work abnormally.
Change-Id: Ic6cd0688287eb4c92c3b27bba4f60c46610c9006
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Sometimes the mclk frequency needs to be set by the external codec
according to the sampling rate, rather than just keeping a fixed
multiple of the sampling rate. In this case, through the property
of "rockchip,mclk-no-set", the SAI will not modify the mclk frequency
again after the codec sets it.
Change-Id: I9bacebb397b9219b773b9953afabd1c5156c8a19
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch removes the two uncommon sampling rates of 12000 and 24000Hz,
because they are not in the definition of SNDRV_PCM_RATE_8000_192000 in
the sound framework:
...
#define SNDRV_PCM_RATE_11025 (1U<<2) /* 11025Hz */
#define SNDRV_PCM_RATE_16000 (1U<<3) /* 16000Hz */
#define SNDRV_PCM_RATE_22050 (1U<<4) /* 22050Hz */
#define SNDRV_PCM_RATE_32000 (1U<<5) /* 32000Hz */
...
According to the configuration of the sampling rate group clock, the
configuration of 11025 and 22050Hz is added. And, it is changed to
select the appropriate mclk in the coeff_clk array according to the
sampling by the codec by default. If you need to use the previous
fixed FS method, you need to specify the property "rockchip,mclk-fs-fixed"
in the dts node.
Change-Id: Iae4478b807f4e6eb88bf6cc9f431ce2f725a5b36
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
In RK3576, DP0 attach to VP1 or VP2 will cause vertical stripe. It
need reset dclk after config stream output to avoid this issue.
Change-Id: I00112e8541828ed53a2ea91e7d79f8d148a7b3df
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
