We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Open pre-emphasize in non-chirp state for rk3228 USB
PHY0 otg port to increase HS slew rate.
Change-Id: Ia565746286a750a251619a83cbbead99c0ddecbd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Make u2phy enter low power mode when suspend. If config the DT of
u2phy port with "rockchip,low-power-mode" property, the port will
be config to lower power state when suspend.
Bvalid irq and linestate irq will be disabled in this mode.
Change-Id: Ie7d40a9a181b0622b1f8d062a741661548cabd59
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Due to usb-phy tuning framework is not added in UPSTREAM codes, so
rk3328 tuning is striped in mainline, this commit make a supplement.
Change-Id: Id8103d65951515b9b21baab14f7125420cea78eb
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch uses a fixed-regulator instead of GPIO pin for
usb vbus power. It doesn't fix any issue, but it makes more
sense to convert the GPIO code into a fixed-regulator.
Change-Id: I7196a9cd592dbb3fab3ef8b9e99babc613a42869
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Most of rockchip SoCs USB 2.0 DP/DM can be bypassed to UART,
it's useful for those platforms without UART interface to
print log via USB interface.
For the time being, we just support for rk312x and rk3399 in
this driver. And we will support for more SoCs in the feature.
With this patch, the user still can't use this bypass function.
It needs to add the property "rockchip,bypass-uart" in the DT
as following:
u2phy0_otg: otg-port {
...
rockchip,bypass-uart;
...
};
And it also needs a special USB cable integrated with an USB
to UART chip.
Note: this function can only be used in debug stage.
Change-Id: Icdab516ff7b327f4a98c3b24bbaf953a605f5278
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The rk312x use different config data which incluce control
register address and value. The patch add config data of
rk312x and match table to support rk3128.
Change-Id: Idd9a5c885cf5e291517e56232e77066eb5d97138
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rk3399 Type-C1 USB 2.0 PHY supports USB BC1.2. This patch
adds registers configuration for Type-C1 USB BC1.2.
With this patch, and set dr_mode of Type-C1 USB to "otg" or
"peripheral" in the DTS, then the Type-C1 USB can detect USB
battery charger.
Change-Id: I2f07ae675cc6066db46e428e6e27045b911a0773
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Let us put phy-port into suspend mode at initialization time for
saving power consumption, and usb controller will resume it during
probe time if needed.
Change-Id: Id3a66af8ff17612d54fbc80db087bf67eaee7726
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds support host-port on rk3368 SoC and amend phy Documentation.
Change-Id: I49a2efe37aad8b34505e4dac08336dc4231f4669
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.
In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.
We only support rk322x/rk3328 to force otg mode for
the time being.
And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.
Usage:
[1] Force host mode
echo host > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo peripheral > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo otg > /sys/devices/platform/<u2phy dev name>/mode
Legacy Usage:
[1] Force host mode
echo 1 > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo 2 > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo 0 > /sys/devices/platform/<u2phy dev name>/mode
Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.
Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.
Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.
CPU 0:
- rockchip_usb2phy_bvalid_irq()
- rockchip_usb2phy_otg_sm_work()
- detect connect to PC usb, do phy power on
- rockchip_usb2phy_power_on()
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- rockchip_usb2phy_power_on()
Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.
Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.
The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.
CPU 0:
- rockchip_chg_detect_work()
- power off phy and start to do charge detection work
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- power on phy again
This race condition may cause charger detection and later usb
enumeration abnormally.
Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.
This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.
Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds amend logic of sm work to compatibly support some legacy SoCs,
because _host_utmi_linestate_ and _host_utmi_hostdisconnect_ GRF status
bits which are required for host sm work were not introduced in these
SoCs.
Change-Id: Ib4f499f592618930ac5016a63b7a530674aa6005
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The usb controller may need to disconnect vbus to trigger disconnect
process or connect vbus to trigger connect interrupt by software. But
current code does not realize the interface. This patch add set mode
function in usb2 phy driver, connect vbus in device mode and disconnect
in other mode.
Change-Id: I49b4180af2f47156a3f4d31f4539f3e444f89a62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The linestate change interrupt may occur during suspend if port is
not connected. This patch pull down dp/dm when suspend.
Change-Id: I31e992727ea63efbda4ecec7ad3af02626eceb44
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.
Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add the new extcon EXTCON_USB_VBUS_EN to enable
vbus output.
Change-Id: I83fb75b2a82ad617dc292967bb4917bbfbcb84cb
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
If detect a SDP charger type, we retry twice more to avoid
DCP falsely identified as SDP due to hardware signal error.
Change-Id: I1bf7bd076cd7767938f6944f1156daa7e64870e4
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds a method to tuning phy with the following
parameters to improve usb driver strength and increase usb2
compatibility.
1. Set max ODT compensation voltage and current tuning reference.
2. Set max pre-emphasis level.
3. Disable the pre-emphasize in eop state and chirp state
to avoid mis-trigger the disconnect detection and also
avoid hs handshake fail.
We don't enable the phy tuning by default. If you want to
tuning phy, you can add a property "rockchip,u2phy-tuning"
in u2phy node, like this:
&u2phy0 {
rockchip,u2phy-tuning;
};
&u2phy1 {
rockchip,u2phy-tuning;
};
Change-Id: Iaa70e2ad3d5d06662be6c05e4d20784e5bb85ae9
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds support usb remote wakeup both host-port and otg-port,
each port can detect linestate irq then wakeup the whole system.
Change-Id: I5efcf958131827548954deb9360b9e98aa4bd0bc
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch does not aim to upstream, just use locally.
If needed, the different SoC can register its own callback function
to tuning the default parameters of phy.
Change-Id: I19b2a4f9e0cb04b139dd64eae1c856fbe9142665
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some platforms (e.g. RK3399 BOX board) otg port connector
interface is not standard, that is a Type-A connector with
vbus always powered on, looks like to work as host mode,
however, the otg port still need to support DRD mode.
In the current code, if otg vbus is always powered on, it
will cause USB2 PHY to detect a floating charger in error
case and power off USB2 PHY. This patch adds a new property
"rockchip,vbus-always-on" to fix this issue. With this patch,
we handle this case as otg host only mode, and avoid to do
charger detection and power off USB2 PHY.
Change-Id: I69e5e87021f3f2d654793e547264aec55ac664ef
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Rockchip USB2 phy provides utmi_avalid and utmi_bvalid for
user to check UTMI vbus status. Generally, both of them can
reflect the vbus status correctly, and the utmi_bvalid has
higher sensitivity, so we select the utmi_bvalid to get vbus
status by default.
But some special SoCs may not provide utmi_bvalid, so we
need to select utmi_avalid in this case.
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I3057704ea2472fe67b3fcdea8ba66e88061b547b
Some EHCI controllers use usic phy,
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The squashfs multi CPU decompressor makes use of get_cpu_ptr() to
acquire a pointer to per-CPU data. get_cpu_ptr() implicitly disables
preemption which serializes the access to the per-CPU data.
But decompression can take quite some time depending on the size. The
observed preempt disabled times in real world scenarios went up to 32ms,
causing massive wakeup latencies. This happens on all CPUs as the
decompression is fully parallelized.
So replace CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU by CONFIG_SQUASHFS_DECOMP_MULTI.
Change-Id: I3fb74bca595ee2345f2f7c276eaf8cc68bcd249b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Like the runtime PM support patch of ohci-platform, we
add the same basic runtime PM for ehci-platform.
Change-Id: I84cbb15dd393e6af69b4cf6887f1628e2cba4999
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Rockchip SoCs such as RV1126 and RK356x requires
4 clocks to be enabled for OHCI.
Change-Id: Ia5202ca7223d95a4b39b1581f740e03ca3f54224
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rk3288 ohci doesn't actually work on hardware, so we
need to disable it in ohci-platform driver.
Change-Id: I72750edda67358ff1e8fe66047bf60420500997e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add a quirk to support rockchip relinquishing port from abnormal ohci
to ehci when FS/LS devices plug in.
To support this function, the rockchip-relinquish-port property must be
specified in ehci node of dt.
Change-Id: I91b58905132282ef2a836d54a1c7ace1e334d119
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Refer to E.2 (P67) of Device Class Definition for Human Interface
Devices V1.11, the bmAttributes field of the standard configuration
descriptor bit 5 should be set if the HID support Remote Wakeup.
This patch enable the usb HID to wake up the system if the HID
supports remote wakeup.
Change-Id: I169c49ff6187b6400b91633332a72964caca1a94
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Extend the existing color management properties to support provision
of a 3D cubic look up table, allowing for color specific adjustments.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Co-developed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Change-Id: I0bda1203a10f0df978b767d29baf06b390c0867e
Link:
https: //lore.kernel.org/dri-devel/20201221015730.28333-4-laurent.pinchart+renesas@ideasonboard.com/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Before vop 2.0, the display sub system only
support one RGB/LVDS/eDP/HDMI/MIPI connector
for one vop, so we can find which output interface
should be enabled by output_type(DPI/LVDS/HDMI).
But for the VOP 2.0 display subsystem, we may
have two connector (LVDS/eDP/HDMI/MIPI) of the
same output_type(HDMI0,HDMI1) enabled at same time,
so the output_type is not enough to give the interface
information, we need to know HDMI0 or HDMI1, eDP0 or eDP1
should be enabled.
So we add output interface id here, every connector
driver should set it correctlly to tell vop driver
to enable the corresponding output interface.
Change-Id: Ic22863f0f18f160b0df7d8f4c3b71b17ef987ea9
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Add the clock tree definition for the new rk1808 SoC.
Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
remove the buf[0] & HYM8563_SEC_VL, it's unsuitable for some hym8563.
set rtc init time for first power on.
Change-Id: Iaa207d554d9df9ad8f138fc2f196c8a7a991b141
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add /proc/clk/
summary: dump clk tree
rate: set clk rate by clk name
enable: enable/disable clk by clk name
parent: set clk parent
Change-Id: Iea0570e74a410a05b3bd29dcd2816dd1320d4ff5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK3568 SoCs have two Temperature Sensors, channel 0 is for CPU,
channel 1 is for GPU.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I0dde1dabfbc1bf44ca203cfdea896ca0c05dfadf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Get the calibration parameters for each chip by reading the OTP,
Calculate temperature using calibration parameters.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I05cfb65ae95dcefc7fc52ed91326c7da9d27de55
RV1126 tsadc bandgap chopper function should be configured,
add a new initialize function to handle this for RV1126 SoCs.
RV1126 tshut mode also need select the tshut type in GRF regs,
add a new set mode function to handle this for RV1126 SoCs.
Change-Id: I81106539362bc32e0d8aaeeb0398d1bcb33b6b60
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RV1126 SOC has two independent Temperature Sensors for CPU and NPU.
RV1126 TSADC clock design has been updated, added the PHY clock,
using the group managed clocks.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I395daa3b591390980a11ea7eed827c0e297f6ebe
Fixed the panic reloads when there are multiple thermal devices.
Change-Id: Ia08b0bfec940be089440b9246cc1abf9626c19a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a new compatible for thermal founding on RV1126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I84e7ca521f4edce9516575bd54709326e62fc85c
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The cpll clk gate bits had an ordering issue. This led to the loss of
the boot sdmmc controller when the gmac was shut down with:
`ip link set eth0 down`
as the cpll_100m was shut off instead of the cpll_62p5.
cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
misplaced.
Fixes: e9ac850b88 ("clk: rockchip: add clock controller for rk3568")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://patchwork.kernel.org/project/linux-clk/patch/20210519174149.3691335-1-pgwipeout@gmail.com/
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I012bdbdc44c4e8de1b42a00c2a9bffb7bd66faef
This patch set attempts to new compatible for thermal founding
on RK1808 SoCs.
Change-Id: I133218cd958e0aabf711a5d22fe5e5da2fbd59ce
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Ieb181ec19dedbbfb7aef474b3558aac867e668eb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tsadc has a tshut pin which is designed to reset the pmic or soc,
when the temperature inside soc is too high. we should switch off
the tshut function and change the pin to gpio function in reboot
process, eg, software reset. If not, the tsadc module will WRONGLY
pull high the tshut pin during its reset process and then WRONGLY
reset the pmic or soc, which incurred a hardware reset. The hardware
reset will reset everything inside soc, even includes the power on
reason flag, which is set by software before reboot process.
we also change over-temperature protection mode to cru mode,
since the tshut pin have be changed to gpio function.
Change-Id: Iac3dacf55a4b5536fccd2eb05a6a9e6923a082c0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
